* [U-Boot] [PATCH] sunxi: video: HDMI: Fix LCD clock divider
@ 2019-08-09 20:30 Mark Kettenis
2019-09-06 18:27 ` Jagan Teki
2019-09-23 18:59 ` Anatolij Gustschin
0 siblings, 2 replies; 3+ messages in thread
From: Mark Kettenis @ 2019-08-09 20:30 UTC (permalink / raw)
To: u-boot
Currently we may end up with an LCD clock divider that differs from
the HDMI PHY clock divider if we can't exactly match the pixel clock.
Fix this by using DIV_ROUND_UP to calculate the divider. This works
since the PLL is chosen such that the resulting pixel clock is
never higher than the requested pixel clock.
Fixes: 1feed358ed15 ("sunxi: video: HDMI: Fix clock setup")
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
---
drivers/video/sunxi/sunxi_dw_hdmi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
index cec23295b5..66a319187c 100644
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -254,7 +254,7 @@ static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid,
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- int div = clock_get_pll3() / edid->pixelclock.typ;
+ int div = DIV_ROUND_UP(clock_get_pll3(), edid->pixelclock.typ);
struct sunxi_lcdc_reg *lcdc;
if (mux == 0) {
--
2.22.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH] sunxi: video: HDMI: Fix LCD clock divider
2019-08-09 20:30 [U-Boot] [PATCH] sunxi: video: HDMI: Fix LCD clock divider Mark Kettenis
@ 2019-09-06 18:27 ` Jagan Teki
2019-09-23 18:59 ` Anatolij Gustschin
1 sibling, 0 replies; 3+ messages in thread
From: Jagan Teki @ 2019-09-06 18:27 UTC (permalink / raw)
To: u-boot
On Sat, Aug 10, 2019 at 2:00 AM Mark Kettenis <kettenis@openbsd.org> wrote:
>
> Currently we may end up with an LCD clock divider that differs from
> the HDMI PHY clock divider if we can't exactly match the pixel clock.
> Fix this by using DIV_ROUND_UP to calculate the divider. This works
> since the PLL is chosen such that the resulting pixel clock is
> never higher than the requested pixel clock.
>
> Fixes: 1feed358ed15 ("sunxi: video: HDMI: Fix clock setup")
>
> Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
> ---
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Moved, to Anatolij on pw
^ permalink raw reply [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH] sunxi: video: HDMI: Fix LCD clock divider
2019-08-09 20:30 [U-Boot] [PATCH] sunxi: video: HDMI: Fix LCD clock divider Mark Kettenis
2019-09-06 18:27 ` Jagan Teki
@ 2019-09-23 18:59 ` Anatolij Gustschin
1 sibling, 0 replies; 3+ messages in thread
From: Anatolij Gustschin @ 2019-09-23 18:59 UTC (permalink / raw)
To: u-boot
On Fri, 9 Aug 2019 22:30:26 +0200
Mark Kettenis kettenis at openbsd.org wrote:
...
> ---
> drivers/video/sunxi/sunxi_dw_hdmi.c | 2 +-
Applied to u-boot-video/master, thanks!
--
Anatolij
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2019-09-23 18:59 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2019-08-09 20:30 [U-Boot] [PATCH] sunxi: video: HDMI: Fix LCD clock divider Mark Kettenis
2019-09-06 18:27 ` Jagan Teki
2019-09-23 18:59 ` Anatolij Gustschin
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