From mboxrd@z Thu Jan  1 00:00:00 1970
From: Miquel Raynal <miquel.raynal@bootlin.com>
Date: Thu, 26 Sep 2019 11:42:31 +0200
Subject: [U-Boot] [PATCH] cmd: mtd: solve bad block support in erase
	command
In-Reply-To: <fa7563df3038453da3bda06da03fb51d@SFHDAG6NODE3.st.com>
References: <20190920072012.17841-1-patrick.delaunay@st.com>
 <e9bfec17-f534-ce8a-fba0-067f8a1c7131@denx.de>
 <fa7563df3038453da3bda06da03fb51d@SFHDAG6NODE3.st.com>
Message-ID: <20190926114231.4b3f0a7b@xps13>
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To: u-boot@lists.denx.de

Hi Patrick,

Patrick DELAUNAY <patrick.delaunay@st.com> wrote on Thu, 26 Sep 2019
09:31:46 +0000:

> Hi Stefan,
>=20
> > From: Stefan Roese <sr@denx.de>
> > Sent: vendredi 20 septembre 2019 11:20
> >=20
> > Hi Patrick,
> >=20
> > On 20.09.19 09:20, Patrick Delaunay wrote: =20
> > > This patch modify the loop in mtd erase command to erase one by one
> > > the blocks in the requested area.
> > >
> > > It solves issue on "mtd erase" command on nand with existing bad
> > > block, the command is interrupted on the first bad block with the tra=
ce:
> > > 	"Skipping bad block at 0xffffffffffffffff"
> > >
> > > In MTD driver (nand/raw), when a bad block is present on the MTD
> > > device, the erase_op.fail_addr is not updated and we have the initial
> > > value MTD_FAIL_ADDR_UNKNOWN =3D (ULL)-1. =20
> >=20
> > So here is the difference? I remember testing this on a board with SPI =
NAND and
> > here it worked correctly. But your test case is with RAW NAND? =20
>=20
> Yes with RAW nand.
>=20
> it is the difference the U-Boot code, for SPI nan use:
> 	int nanddev_mtd_erase()
>=20
> the fail address is always updated=20
> 	=3D> einfo->fail_addr =3D nanddev_pos_to_offs(nand, &pos); =20
>=20
> =20
> > Do you have a change to also test this on a board with SPI NAND? =20
>=20
> I do the test  a SPI-NAND today.
>=20
> The mtd erase command was functional on SPI-ANND before my patch :=20
> I create 2 bad block manually and they are correctly skipped.
>=20
> STM32MP> mtd list   =20
> List of MTD devices:
> * spi-nand0
>   - device: spi-nand at 0
>   - parent: qspi at 58003000
>   - driver: spi_nand
>   - type: NAND flash
>   - block size: 0x20000 bytes
>   - min I/O: 0x800 bytes
>   - OOB size: 128 bytes
>   - OOB available: 62 bytes
>   - 0x000000000000-0x000010000000 : "spi-nand0"
> 	  - 0x000000000000-0x000000200000 : "fsbl"
> 	  - 0x000000200000-0x000000400000 : "ssbl1"
> 	  - 0x000000400000-0x000000600000 : "ssbl2"
> 	  - 0x000000600000-0x000010000000 : "UBI"
>=20
> STM32MP> mtd erase spi-nand0 0x00000000 0x10000000             =20
> Erasing 0x00000000 ... 0x0fffffff (2048 eraseblock(s))
> 0x0fd00000: bad block
> 0x0fd20000: bad block
> attempt to erase a bad/reserved block @fd00000
> Skipping bad block at 0x0fd00000
> attempt to erase a bad/reserved block @fd20000
> Skipping bad block at 0x0fd20000
> 0x0fd00000: bad block
> 0x0fd20000: bad block
>=20
>=20
> > Thanks,
> > Stefan
> >  =20
>=20
> What it is the better solution for you ?
>=20
>  update the MTD command (my patch) or allign the behavior of the 2 MTD de=
vices=20
> - MTD RAW NAND (nand_base.c:: nand_erase_nand)
> - MTD SPI NAND (core.c:: nanddev_mtd_erase)

Do you think it is easy to make use of nanddev_mtd_erase() from the raw
NAND core? It is probably a little bit more elegant (and efficient)
to do all in one go than iterating over each block (while there is a
helper in the core to do that).


Thanks,
Miqu=C3=A8l