From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Sat, 12 Oct 2019 16:25:21 -0400 Subject: [U-Boot] [PATCH v2 14/26] arm: dts: k3-j721e-main: Add C66x DSP nodes In-Reply-To: <20190904103151.20121-15-lokeshvutla@ti.com> References: <20190904103151.20121-1-lokeshvutla@ti.com> <20190904103151.20121-15-lokeshvutla@ti.com> Message-ID: <20191012202521.GA16029@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Wed, Sep 04, 2019 at 04:01:39PM +0530, Lokesh Vutla wrote: > The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs) > in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP > Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional > 288 KB of L2 configurable SRAM/Cache. These subsystems do not have > an MMU but contain a Region Address Translator (RAT) sub-module for > translating 32-bit processor addresses into larger bus addresses. > The inter-processor communication between the main A72 cores and > these processors is achieved through shared memory and Mailboxes. > Add the DT nodes for these DSP processor sub-systems in the common > k3-j721e-main.dtsi file. > > Signed-off-by: Suman Anna > Signed-off-by: Lokesh Vutla Applied to u-boot/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 833 bytes Desc: not available URL: