From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Sat, 12 Oct 2019 16:25:31 -0400 Subject: [U-Boot] [PATCH v2 16/26] arm: dts: k3-am65-mcu: Add MCU domain R5F DT nodes In-Reply-To: <20190904103151.20121-17-lokeshvutla@ti.com> References: <20190904103151.20121-1-lokeshvutla@ti.com> <20190904103151.20121-17-lokeshvutla@ti.com> Message-ID: <20191012202531.GC16029@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Wed, Sep 04, 2019 at 04:01:41PM +0530, Lokesh Vutla wrote: > From: Suman Anna > > The AM65x SoCs has a single dual-core Arm Cortex-R5F processor > subsystem/cluster (MCU_R5FSS0) within the MCU domain. This cluster > can be configured at boot time to be either run in a LockStep mode > or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. > This subsystem has 64 KB each Tightly-Coupled Memory (TCM) internal > memories for each core split between two banks - ATCM and BTCM > (further interleaved into two banks). There are some IP integration > differences from standard Arm R5 clusters such as the absence of > an ACP port, presence of an additional TI-specific Region Address > Translater (RAT) module for translating 32-bit CPU addresses into > larger system bus addresses etc. > > Add the DT node for the MCU domain R5F cluster/subsystem, the two > R5 cores are added as child nodes to the main cluster/subsystem node. > The cluster is configured to run in Split-mode by default, with the > ATCMs enabled to allow the R5 cores to execute code from DDR with > boot-strapping code from ATCM. The inter-processor communication > between the main A72 cores and these processors is achieved through > shared memory and Mailboxes. > > Signed-off-by: Suman Anna > Signed-off-by: Lokesh Vutla Applied to u-boot/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 833 bytes Desc: not available URL: