* [U-Boot] [PATCH v2 1/6] mx7ulp: Print the LDO mode status
@ 2019-10-30 13:41 Fabio Estevam
2019-10-30 13:41 ` [U-Boot] [PATCH v2 2/6] mx7ulp: Introduce the CONFIG_LDO_ENABLED_MODE option Fabio Estevam
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Fabio Estevam @ 2019-10-30 13:41 UTC (permalink / raw)
To: u-boot
As per the i.MX7ULP datasheet, it can boot in LDO enabled mode
or LDO bypass mode.
Print the LDO mode status in the U-Boot log for convenience.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
Changes since v1:
- None
arch/arm/mach-imx/mx7ulp/soc.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index 127fcfeea1..b9a108a514 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -131,6 +131,21 @@ const char *get_imx_type(u32 imxtype)
return "7ULP";
}
+#define PMC0_BASE_ADDR 0x410a1000
+#define PMC0_CTRL 0x28
+#define PMC0_CTRL_LDOEN BIT(31)
+
+static bool ldo_mode_is_enabled(void)
+{
+ unsigned int reg;
+
+ reg = readl(PMC0_BASE_ADDR + PMC0_CTRL);
+ if (reg & PMC0_CTRL_LDOEN)
+ return true;
+ else
+ return false;
+}
+
int print_cpuinfo(void)
{
u32 cpurev;
@@ -159,6 +174,11 @@ int print_cpuinfo(void)
break;
}
+ if (ldo_mode_is_enabled())
+ printf("PMC1: LDO enabled mode\n");
+ else
+ printf("PMC1: LDO bypass mode\n");
+
return 0;
}
#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v2 2/6] mx7ulp: Introduce the CONFIG_LDO_ENABLED_MODE option
2019-10-30 13:41 [U-Boot] [PATCH v2 1/6] mx7ulp: Print the LDO mode status Fabio Estevam
@ 2019-10-30 13:41 ` Fabio Estevam
2019-10-30 13:41 ` [U-Boot] [PATCH v2 3/6] mx7ulp: Remove the _RUN notation from the PMC1 LDOVL definitions Fabio Estevam
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Fabio Estevam @ 2019-10-30 13:41 UTC (permalink / raw)
To: u-boot
Introduce the CONFIG_LDO_ENABLED_MODE option so that i.MX7ULP boards
designed to operate with LDO enabled mode can work with 0.95V at LDO
output in RUN mode as per the datasheet.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
Changes since v1:
- None
arch/arm/mach-imx/mx7ulp/Kconfig | 5 +++
arch/arm/mach-imx/mx7ulp/soc.c | 58 ++++++++++++++++++++++++++++++++
2 files changed, 63 insertions(+)
diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig
index ed5f0aeb2d..138c58363f 100644
--- a/arch/arm/mach-imx/mx7ulp/Kconfig
+++ b/arch/arm/mach-imx/mx7ulp/Kconfig
@@ -3,6 +3,11 @@ if ARCH_MX7ULP
config SYS_SOC
default "mx7ulp"
+config LDO_ENABLED_MODE
+ bool "i.MX7ULP LDO Enabled Mode"
+ help
+ Select this option to enable the PMC1 LDO.
+
config MX7ULP
bool
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index b9a108a514..751575c95e 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -9,6 +9,22 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/hab.h>
+#define PMC0_BASE_ADDR 0x410a1000
+#define PMC0_CTRL 0x28
+#define PMC0_CTRL_LDOEN BIT(31)
+#define PMC0_CTRL_LDOOKDIS BIT(30)
+#define PMC0_CTRL_PMC1ON BIT(24)
+#define PMC1_BASE_ADDR 0x40400000
+#define PMC1_RUN 0x8
+#define PMC1_STOP 0x10
+#define PMC1_VLPS 0x14
+#define PMC1_RUN_LDOVL_SHIFT 16
+#define PMC1_RUN_LDOVL_MASK (0x3f << PMC1_RUN_LDOVL_SHIFT)
+#define PMC1_RUN_LDOVL_900 0x1e
+#define PMC1_RUN_LDOVL_950 0x23
+#define PMC1_STATUS 0x20
+#define PMC1_STATUS_LDOVLF BIT(8)
+
static char *get_reset_cause(char *);
#if defined(CONFIG_IMX_HAB)
@@ -100,6 +116,44 @@ void init_wdog(void)
disable_wdog(WDG2_RBASE);
}
+#if defined(CONFIG_LDO_ENABLED_MODE)
+static void init_ldo_mode(void)
+{
+ unsigned int reg;
+
+ /* Set LDOOKDIS */
+ setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS);
+
+ /* Set LDOVL to 0.95V in PMC1_RUN */
+ reg = readl(PMC1_BASE_ADDR + PMC1_RUN);
+ reg &= ~PMC1_RUN_LDOVL_MASK;
+ reg |= (PMC1_RUN_LDOVL_950 << PMC1_RUN_LDOVL_SHIFT);
+ writel(PMC1_BASE_ADDR + PMC1_RUN, reg);
+
+ /* Wait for LDOVLF to be cleared */
+ reg = readl(PMC1_BASE_ADDR + PMC1_STATUS);
+ while (reg & PMC1_STATUS_LDOVLF)
+ ;
+
+ /* Set LDOVL to 0.95V in PMC1_STOP */
+ reg = readl(PMC1_BASE_ADDR + PMC1_STOP);
+ reg &= ~PMC1_RUN_LDOVL_MASK;
+ reg |= (PMC1_RUN_LDOVL_950 << PMC1_RUN_LDOVL_SHIFT);
+ writel(PMC1_BASE_ADDR + PMC1_STOP, reg);
+
+ /* Set LDOVL to 0.90V in PMC1_VLPS */
+ reg = readl(PMC1_BASE_ADDR + PMC1_VLPS);
+ reg &= ~PMC1_RUN_LDOVL_MASK;
+ reg |= (PMC1_RUN_LDOVL_900 << PMC1_RUN_LDOVL_SHIFT);
+ writel(PMC1_BASE_ADDR + PMC1_VLPS, reg);
+
+ /* Set LDOEN bit */
+ setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN);
+
+ /* Set the PMC1ON bit */
+ setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON);
+}
+#endif
void s_init(void)
{
@@ -113,6 +167,10 @@ void s_init(void)
/* enable dumb pmic */
writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR);
}
+
+#if defined(CONFIG_LDO_ENABLED_MODE)
+ init_ldo_mode();
+#endif
return;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v2 3/6] mx7ulp: Remove the _RUN notation from the PMC1 LDOVL definitions
2019-10-30 13:41 [U-Boot] [PATCH v2 1/6] mx7ulp: Print the LDO mode status Fabio Estevam
2019-10-30 13:41 ` [U-Boot] [PATCH v2 2/6] mx7ulp: Introduce the CONFIG_LDO_ENABLED_MODE option Fabio Estevam
@ 2019-10-30 13:41 ` Fabio Estevam
2019-10-30 13:41 ` [U-Boot] [PATCH v2 4/6] mx7ulp: scg: Remove unnused scg_a7_apll_init() Fabio Estevam
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Fabio Estevam @ 2019-10-30 13:41 UTC (permalink / raw)
To: u-boot
The LDOVL definitions is common to all the modes, not only RUN mode,
so in order to avoid confusion, remove the _RUN notation from the PMC1
LDOVL definitions.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
Changes since v1:
- None
arch/arm/mach-imx/mx7ulp/soc.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index 751575c95e..4487fa61c0 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -18,10 +18,10 @@
#define PMC1_RUN 0x8
#define PMC1_STOP 0x10
#define PMC1_VLPS 0x14
-#define PMC1_RUN_LDOVL_SHIFT 16
-#define PMC1_RUN_LDOVL_MASK (0x3f << PMC1_RUN_LDOVL_SHIFT)
-#define PMC1_RUN_LDOVL_900 0x1e
-#define PMC1_RUN_LDOVL_950 0x23
+#define PMC1_LDOVL_SHIFT 16
+#define PMC1_LDOVL_MASK (0x3f << PMC1_LDOVL_SHIFT)
+#define PMC1_LDOVL_900 0x1e
+#define PMC1_LDOVL_950 0x23
#define PMC1_STATUS 0x20
#define PMC1_STATUS_LDOVLF BIT(8)
@@ -126,8 +126,8 @@ static void init_ldo_mode(void)
/* Set LDOVL to 0.95V in PMC1_RUN */
reg = readl(PMC1_BASE_ADDR + PMC1_RUN);
- reg &= ~PMC1_RUN_LDOVL_MASK;
- reg |= (PMC1_RUN_LDOVL_950 << PMC1_RUN_LDOVL_SHIFT);
+ reg &= ~PMC1_LDOVL_MASK;
+ reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
writel(PMC1_BASE_ADDR + PMC1_RUN, reg);
/* Wait for LDOVLF to be cleared */
@@ -137,14 +137,14 @@ static void init_ldo_mode(void)
/* Set LDOVL to 0.95V in PMC1_STOP */
reg = readl(PMC1_BASE_ADDR + PMC1_STOP);
- reg &= ~PMC1_RUN_LDOVL_MASK;
- reg |= (PMC1_RUN_LDOVL_950 << PMC1_RUN_LDOVL_SHIFT);
+ reg &= ~PMC1_LDOVL_MASK;
+ reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
writel(PMC1_BASE_ADDR + PMC1_STOP, reg);
/* Set LDOVL to 0.90V in PMC1_VLPS */
reg = readl(PMC1_BASE_ADDR + PMC1_VLPS);
- reg &= ~PMC1_RUN_LDOVL_MASK;
- reg |= (PMC1_RUN_LDOVL_900 << PMC1_RUN_LDOVL_SHIFT);
+ reg &= ~PMC1_LDOVL_MASK;
+ reg |= (PMC1_LDOVL_900 << PMC1_LDOVL_SHIFT);
writel(PMC1_BASE_ADDR + PMC1_VLPS, reg);
/* Set LDOEN bit */
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v2 4/6] mx7ulp: scg: Remove unnused scg_a7_apll_init()
2019-10-30 13:41 [U-Boot] [PATCH v2 1/6] mx7ulp: Print the LDO mode status Fabio Estevam
2019-10-30 13:41 ` [U-Boot] [PATCH v2 2/6] mx7ulp: Introduce the CONFIG_LDO_ENABLED_MODE option Fabio Estevam
2019-10-30 13:41 ` [U-Boot] [PATCH v2 3/6] mx7ulp: Remove the _RUN notation from the PMC1 LDOVL definitions Fabio Estevam
@ 2019-10-30 13:41 ` Fabio Estevam
2019-10-30 13:41 ` [U-Boot] [PATCH v2 5/6] mx7ulp: Sync the device tree related files Fabio Estevam
2019-10-30 13:41 ` [U-Boot] [PATCH v2 6/6] mx7ulp: Add support for Embedded Artists COM board Fabio Estevam
4 siblings, 0 replies; 8+ messages in thread
From: Fabio Estevam @ 2019-10-30 13:41 UTC (permalink / raw)
To: u-boot
scg_a7_apll_init() is not called anywhere, so remove such dead code
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
Changes since v1:
- None
arch/arm/include/asm/arch-mx7ulp/scg.h | 1 -
arch/arm/mach-imx/mx7ulp/scg.c | 61 --------------------------
2 files changed, 62 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx7ulp/scg.h b/arch/arm/include/asm/arch-mx7ulp/scg.h
index 531d8f3a95..b79bde338f 100644
--- a/arch/arm/include/asm/arch-mx7ulp/scg.h
+++ b/arch/arm/include/asm/arch-mx7ulp/scg.h
@@ -331,7 +331,6 @@ u32 decode_pll(enum pll_clocks pll);
void scg_a7_rccr_init(void);
void scg_a7_spll_init(void);
void scg_a7_ddrclk_init(void);
-void scg_a7_apll_init(void);
void scg_a7_firc_init(void);
void scg_a7_nicclk_init(void);
void scg_a7_sys_clk_sel(enum scg_sys_src clk);
diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c
index 819c90af6c..c7bb7a1c66 100644
--- a/arch/arm/mach-imx/mx7ulp/scg.c
+++ b/arch/arm/mach-imx/mx7ulp/scg.c
@@ -949,67 +949,6 @@ void scg_a7_ddrclk_init(void)
/* Clock source is System OSC <<0 */
#define SCG1_APLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT)
-/*
- * A7 APLL = 24MHz / 1 * 22 / 1 / 1 = 528MHz,
- * system PLL is sourced from APLL,
- * APLL clock source is system OSC (24MHz)
- */
-#define SCG1_APLL_CFG_NUM_24M_OSC (SCG1_APLL_CFG_POSTDIV2_NUM | \
- SCG1_APLL_CFG_POSTDIV1_NUM | \
- (22 << SCG_PLL_CFG_MULT_SHIFT) | \
- SCG1_APLL_CFG_PFDSEL_NUM | \
- SCG1_APLL_CFG_PREDIV_NUM | \
- SCG1_APLL_CFG_BYPASS_NUM | \
- SCG1_APLL_CFG_PLLSEL_NUM | \
- SCG1_APLL_CFG_CLKSRC_NUM)
-
-/* PFD0 Freq = A7 APLL(528MHz) * 18 / 27 = 352MHz */
-#define SCG1_APLL_PFD0_FRAC_NUM (27)
-
-
-void scg_a7_apll_init(void)
-{
- u32 val = 0;
-
- /* Disable A7 Auxiliary PLL */
- val = readl(&scg1_regs->apllcsr);
- val &= ~SCG_APLL_CSR_APLLEN_MASK;
- writel(val, &scg1_regs->apllcsr);
-
- /* Gate off A7 APLL PFD0 ~ PDF4 */
- val = readl(&scg1_regs->apllpfd);
- val |= 0x80808080;
- writel(val, &scg1_regs->apllpfd);
-
- /* ================ A7 APLL Configuration Start ============== */
- /* Configure A7 Auxiliary PLL */
- writel(SCG1_APLL_CFG_NUM_24M_OSC, &scg1_regs->apllcfg);
-
- /* Enable A7 Auxiliary PLL */
- val = readl(&scg1_regs->apllcsr);
- val |= SCG_APLL_CSR_APLLEN_MASK;
- writel(val, &scg1_regs->apllcsr);
-
- /* Wait for A7 APLL clock ready */
- while (!(readl(&scg1_regs->apllcsr) & SCG_APLL_CSR_APLLVLD_MASK))
- ;
-
- /* Configure A7 APLL PFD0 */
- val = readl(&scg1_regs->apllpfd);
- val &= ~SCG_PLL_PFD0_FRAC_MASK;
- val |= SCG1_APLL_PFD0_FRAC_NUM;
- writel(val, &scg1_regs->apllpfd);
-
- /* Un-gate A7 APLL PFD0 */
- val = readl(&scg1_regs->apllpfd);
- val &= ~SCG_PLL_PFD0_GATE_MASK;
- writel(val, &scg1_regs->apllpfd);
-
- /* Wait for A7 APLL PFD0 clock being valid */
- while (!(readl(&scg1_regs->apllpfd) & SCG_PLL_PFD0_VALID_MASK))
- ;
-}
-
/* SCG1(A7) FIRC DIV configurations */
/* Disable FIRC DIV3 */
#define SCG1_FIRCDIV_DIV3_NUM ((0x0) << SCG_FIRCDIV_DIV3_SHIFT)
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v2 5/6] mx7ulp: Sync the device tree related files
2019-10-30 13:41 [U-Boot] [PATCH v2 1/6] mx7ulp: Print the LDO mode status Fabio Estevam
` (2 preceding siblings ...)
2019-10-30 13:41 ` [U-Boot] [PATCH v2 4/6] mx7ulp: scg: Remove unnused scg_a7_apll_init() Fabio Estevam
@ 2019-10-30 13:41 ` Fabio Estevam
2019-10-30 13:41 ` [U-Boot] [PATCH v2 6/6] mx7ulp: Add support for Embedded Artists COM board Fabio Estevam
4 siblings, 0 replies; 8+ messages in thread
From: Fabio Estevam @ 2019-10-30 13:41 UTC (permalink / raw)
To: u-boot
Sync the mx7ulp device tree related files with the one from
NXP U-Boot vendor tree (imx_v2019.04_4.19.35_1.0.0).
The mainline support for i.MX7ULP is very premature at this stage.
We should probably re-sync with mainline Linux dts when it gets
in better shape, but for now sync with the U-Boot vendor code.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
Changes since v1:
- None
arch/arm/dts/imx7ulp-evk.dts | 157 ++-
arch/arm/dts/imx7ulp-pinfunc.h | 1748 ++++++++++++++++----------------
arch/arm/dts/imx7ulp.dtsi | 28 +-
3 files changed, 969 insertions(+), 964 deletions(-)
diff --git a/arch/arm/dts/imx7ulp-evk.dts b/arch/arm/dts/imx7ulp-evk.dts
index e56b7226e6..08a682f314 100644
--- a/arch/arm/dts/imx7ulp-evk.dts
+++ b/arch/arm/dts/imx7ulp-evk.dts
@@ -15,7 +15,7 @@
compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";
chosen {
- bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200";
+ bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0000,115200";
stdout-path = &lpuart4;
};
@@ -66,7 +66,7 @@
compatible = "regulator-fixed";
reg = <0>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb_otg1>;
+ pinctrl-0 = <&pinctrl_usbotg1_vbus>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@@ -84,22 +84,6 @@
enable-active-high;
};
- reg_vsd_3v3b: regulator at 2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "VSD_3V3B";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
- };
-
- extcon_usb1: extcon_usb1 {
- compatible = "linux,extcon-usb-gpio";
- id-gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_extcon_usb1>;
};
pf1550-rpmsg {
@@ -166,134 +150,135 @@
imx7ulp-evk {
pinctrl_hog_1: hoggrp-1 {
fsl,pins = <
- ULP1_PAD_PTC10__PTC10 0x30100 /* USDHC0 CD */
- ULP1_PAD_PTC1__PTC1 0x20100
- ULP1_PAD_PTD0__PTD0 0x30100 /* USDHC0 RST */
- ULP1_PAD_PTE13__PTE13 0x30103 /* USDHC1 CD */
- ULP1_PAD_PTE12__PTE12 0x30103 /* USDHC1 WP */
- ULP1_PAD_PTE14__SDHC1_VS 0x843 /* USDHC1 VSEL */
+ IMX7ULP_PAD_PTC1__PTC1 0x20000
>;
};
pinctrl_backlight: backlight_grp {
fsl,pins = <
- ULP1_PAD_PTF2__PTF2 0x20100
+ IMX7ULP_PAD_PTF2__PTF2 0x20100
>;
};
pinctrl_lpi2c5: lpi2c5grp {
fsl,pins = <
- ULP1_PAD_PTC4__LPI2C5_SCL 0x527
- ULP1_PAD_PTC5__LPI2C5_SDA 0x527
+ IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x27
+ IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x27
>;
};
pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp {
fsl,pins = <
- ULP1_PAD_PTC19__PTC19 0x20103
+ IMX7ULP_PAD_PTC19__PTC19 0x20003
>;
};
pinctrl_lpuart4: lpuart4grp {
fsl,pins = <
- ULP1_PAD_PTC3__LPUART4_RX 0x400
- ULP1_PAD_PTC2__LPUART4_TX 0x400
+ IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
+ IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
>;
};
pinctrl_lpuart6: lpuart6grp {
fsl,pins = <
- ULP1_PAD_PTE10__LPUART6_TX 0x400
- ULP1_PAD_PTE11__LPUART6_RX 0x400
- ULP1_PAD_PTE9__LPUART6_RTS_B 0x400
- ULP1_PAD_PTE8__LPUART6_CTS_B 0x400
- ULP1_PAD_PTE7__PTE7 0x00 /* BT_REG_ON */
+ IMX7ULP_PAD_PTE10__LPUART6_TX 0x3
+ IMX7ULP_PAD_PTE11__LPUART6_RX 0x3
+ IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x3
+ IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x3
+ IMX7ULP_PAD_PTE7__PTE7 0x20000 /* BT_REG_ON */
>;
};
pinctrl_lpuart7: lpuart7grp {
fsl,pins = <
- ULP1_PAD_PTF14__LPUART7_TX 0x400
- ULP1_PAD_PTF15__LPUART7_RX 0x400
- ULP1_PAD_PTF13__LPUART7_RTS_B 0x400
- ULP1_PAD_PTF12__LPUART7_CTS_B 0x400
+ IMX7ULP_PAD_PTF14__LPUART7_TX 0x3
+ IMX7ULP_PAD_PTF15__LPUART7_RX 0x3
+ IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x3
+ IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x3
>;
};
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
- ULP1_PAD_PTD1__SDHC0_CMD 0x843
- ULP1_PAD_PTD2__SDHC0_CLK 0x10843
- ULP1_PAD_PTD7__SDHC0_D3 0x843
- ULP1_PAD_PTD8__SDHC0_D2 0x843
- ULP1_PAD_PTD9__SDHC0_D1 0x843
- ULP1_PAD_PTD10__SDHC0_D0 0x843
+ IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
+ IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
+ IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
+ IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
+ IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
+ IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
+ IMX7ULP_PAD_PTC10__PTC10 0x10000 /* USDHC0 CD */
+ IMX7ULP_PAD_PTD0__PTD0 0x20000 /* USDHC0 RST */
>;
};
pinctrl_usdhc0_8bit: usdhc0grp_8bit {
fsl,pins = <
- ULP1_PAD_PTD1__SDHC0_CMD 0x843
- ULP1_PAD_PTD2__SDHC0_CLK 0x843
- ULP1_PAD_PTD3__SDHC0_D7 0x843
- ULP1_PAD_PTD4__SDHC0_D6 0x843
- ULP1_PAD_PTD5__SDHC0_D5 0x843
- ULP1_PAD_PTD6__SDHC0_D4 0x843
- ULP1_PAD_PTD7__SDHC0_D3 0x843
- ULP1_PAD_PTD8__SDHC0_D2 0x843
- ULP1_PAD_PTD9__SDHC0_D1 0x843
- ULP1_PAD_PTD10__SDHC0_D0 0x843
+ IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
+ IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
+ IMX7ULP_PAD_PTD3__SDHC0_D7 0x43
+ IMX7ULP_PAD_PTD4__SDHC0_D6 0x43
+ IMX7ULP_PAD_PTD5__SDHC0_D5 0x43
+ IMX7ULP_PAD_PTD6__SDHC0_D4 0x43
+ IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
+ IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
+ IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
+ IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
+ IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42
>;
};
pinctrl_lpi2c7: lpi2c7grp {
fsl,pins = <
- ULP1_PAD_PTF12__LPI2C7_SCL 0x527
- ULP1_PAD_PTF13__LPI2C7_SDA 0x527
+ IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x27
+ IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x27
>;
};
pinctrl_lpspi3: lpspi3grp {
fsl,pins = <
- ULP1_PAD_PTF16__LPSPI3_SIN 0x300
- ULP1_PAD_PTF17__LPSPI3_SOUT 0x300
- ULP1_PAD_PTF18__LPSPI3_SCK 0x300
- ULP1_PAD_PTF19__LPSPI3_PCS0 0x300
+ IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x0
+ IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x0
+ IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x0
+ IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x0
>;
};
- pinctrl_usb_otg1: usbotg1grp {
+ pinctrl_usbotg1_vbus: otg1vbusgrp {
fsl,pins = <
- ULP1_PAD_PTC0__PTC0 0x30100
+ IMX7ULP_PAD_PTC0__PTC0 0x20000
>;
};
- pinctrl_extcon_usb1: extcon1grp {
+ pinctrl_usbotg1_id: otg1idgrp {
fsl,pins = <
- ULP1_PAD_PTC8__PTC8 0x30103
+ IMX7ULP_PAD_PTC13__USB0_ID 0x10003
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
- ULP1_PAD_PTE3__SDHC1_CMD 0x843
- ULP1_PAD_PTE2__SDHC1_CLK 0x843
- ULP1_PAD_PTE1__SDHC1_D0 0x843
- ULP1_PAD_PTE0__SDHC1_D1 0x843
- ULP1_PAD_PTE5__SDHC1_D2 0x843
- ULP1_PAD_PTE4__SDHC1_D3 0x843
+ IMX7ULP_PAD_PTE3__SDHC1_CMD 0x43
+ IMX7ULP_PAD_PTE2__SDHC1_CLK 0x10042
+ IMX7ULP_PAD_PTE1__SDHC1_D0 0x43
+ IMX7ULP_PAD_PTE0__SDHC1_D1 0x43
+ IMX7ULP_PAD_PTE5__SDHC1_D2 0x43
+ IMX7ULP_PAD_PTE4__SDHC1_D3 0x43
>;
};
pinctrl_usdhc1_rst: usdhc1grp_rst {
fsl,pins = <
- ULP1_PAD_PTE11__PTE11 0x30100 /* USDHC1 RST */
+ IMX7ULP_PAD_PTE11__PTE11 0x20000 /* USDHC1 RST */
+ IMX7ULP_PAD_PTE13__PTE13 0x10003 /* USDHC1 CD */
+ IMX7ULP_PAD_PTE12__PTE12 0x10003 /* USDHC1 WP */
+ IMX7ULP_PAD_PTE14__SDHC1_VS 0x43 /* USDHC1 VSEL */
>;
};
- pinctrl_wifi: wifigrp {
+ pinctrl_dsi_hdmi: dsi_hdmi_grp {
fsl,pins = <
- ULP1_PAD_PTE6__PTE6 0x43 /* WL_REG_ON */
+ IMX7ULP_PAD_PTC18__PTC18 0x10003 /* DSI_HDMI_INT */
>;
};
};
@@ -304,7 +289,7 @@
disp-dev = "mipi_dsi_northwest";
display = <&display0>;
- display0: display {
+ display0: display at 0 {
bits-per-pixel = <16>;
bus-width = <24>;
@@ -343,21 +328,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c5>;
status = "okay";
-
- fxas2100x at 20 {
- compatible = "fsl,fxas2100x";
- reg = <0x20>;
- };
-
- fxos8700 at 1e {
- compatible = "fsl,fxos8700";
- reg = <0x1e>;
- };
-
- mpl3115 at 60 {
- compatible = "fsl,mpl3115";
- reg = <0x60>;
- };
};
&lpspi3 {
@@ -406,13 +376,18 @@
&usbotg1 {
vbus-supply = <®_usb_otg1_vbus>;
- extcon = <0>, <&extcon_usb1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_id>;
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};
+&usbphy1 {
+ fsl,tx-d-cal = <88>;
+};
+
&usdhc0 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc0>;
diff --git a/arch/arm/dts/imx7ulp-pinfunc.h b/arch/arm/dts/imx7ulp-pinfunc.h
index b1b6a71f2c..777d7f0947 100644
--- a/arch/arm/dts/imx7ulp-pinfunc.h
+++ b/arch/arm/dts/imx7ulp-pinfunc.h
@@ -1,5 +1,6 @@
/*
- * Copyright 2014 - 2015 Freescale Semiconductor, Inc.
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 - 2018 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -7,876 +8,885 @@
*
*/
-#ifndef __DTS_ULP1_PINFUNC_H
-#define __DTS_ULP1_PINFUNC_H
+#ifndef __DTS_IMX7ULP_PINFUNC_H
+#define __DTS_IMX7ULP_PINFUNC_H
/*
* The pin function ID is a tuple of
- * <mux_conf_reg mux2_reg mux_mode mux2_val>
- *
- * !!! IMPORTANT NOTE !!!
- *
- * There's common mux_reg & conf_reg register for each pad on ULP1 device, so the first
- * two values are defined as same value. Extra non-zero mux2_reg value within the tuple
- * means that there's additional mux2 control register that must be configured to
- * mux2_val accordingly to fetch desired pin functionality on ULP1 device.
- *
+ * <mux_conf_reg input_reg mux_mode input_val>
*/
+#define IMX7ULP_PAD_PTA0__CMP0_IN1_3V 0x0000 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA0__PTA0 0x0000 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA0__LPSPI0_PCS1 0x0000 0x0104 0x3 0x2
+#define IMX7ULP_PAD_PTA0__LPUART0_CTS_B 0x0000 0x01F8 0x4 0x2
+#define IMX7ULP_PAD_PTA0__LPI2C0_SCL 0x0000 0x017C 0x5 0x2
+#define IMX7ULP_PAD_PTA0__TPM0_CLKIN 0x0000 0x01A8 0x6 0x2
+#define IMX7ULP_PAD_PTA0__I2S0_RX_BCLK 0x0000 0x01B8 0x7 0x2
+#define IMX7ULP_PAD_PTA0__LLWU0_P0 0x0000 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTA1__CMP0_IN2_3V 0x0004 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA1__LPSPI0_PCS2 0x0004 0x0108 0x3 0x1
+#define IMX7ULP_PAD_PTA1__LPUART0_RTS_B 0x0004 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTA1__LPI2C0_SDA 0x0004 0x0180 0x5 0x1
+#define IMX7ULP_PAD_PTA1__TPM0_CH0 0x0004 0x0138 0x6 0x1
+#define IMX7ULP_PAD_PTA1__I2S0_RX_FS 0x0004 0x01BC 0x7 0x1
+#define IMX7ULP_PAD_PTA2__CMP1_IN2_3V 0x0008 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA2__PTA2 0x0008 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA2__LPSPI0_PCS3 0x0008 0x010C 0x3 0x1
+#define IMX7ULP_PAD_PTA2__LPUART0_TX 0x0008 0x0200 0x4 0x1
+#define IMX7ULP_PAD_PTA2__LPI2C0_HREQ 0x0008 0x0178 0x5 0x1
+#define IMX7ULP_PAD_PTA2__TPM0_CH1 0x0008 0x013C 0x6 0x1
+#define IMX7ULP_PAD_PTA2__I2S0_RXD0 0x0008 0x01DC 0x7 0x1
+#define IMX7ULP_PAD_PTA3__CMP1_IN4_3V 0x000C 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA3__PTA3 0x000C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA3__LPSPI0_PCS0 0x000C 0x0100 0x3 0x1
+#define IMX7ULP_PAD_PTA3__LPUART0_RX 0x000C 0x01FC 0x4 0x1
+#define IMX7ULP_PAD_PTA3__TPM0_CH2 0x000C 0x0140 0x6 0x1
+#define IMX7ULP_PAD_PTA3__I2S0_RXD1 0x000C 0x01E0 0x7 0x1
+#define IMX7ULP_PAD_PTA3__CMP0_OUT 0x000C 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTA3__LLWU0_P1 0x000C 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTA4__ADC1_CH3A 0x0010 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA4__PTA4 0x0010 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA4__LPSPI0_SIN 0x0010 0x0114 0x3 0x1
+#define IMX7ULP_PAD_PTA4__LPUART1_CTS_B 0x0010 0x0204 0x4 0x1
+#define IMX7ULP_PAD_PTA4__LPI2C1_SCL 0x0010 0x0188 0x5 0x1
+#define IMX7ULP_PAD_PTA4__TPM0_CH3 0x0010 0x0144 0x6 0x1
+#define IMX7ULP_PAD_PTA4__I2S0_MCLK 0x0010 0x01B4 0x7 0x1
+#define IMX7ULP_PAD_PTA5__ADC1_CH3B 0x0014 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA5__PTA5 0x0014 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA5__LPSPI0_SOUT 0x0014 0x0118 0x3 0x1
+#define IMX7ULP_PAD_PTA5__LPUART1_RTS_B 0x0014 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTA5__LPI2C1_SDA 0x0014 0x018C 0x5 0x1
+#define IMX7ULP_PAD_PTA5__TPM0_CH4 0x0014 0x0148 0x6 0x1
+#define IMX7ULP_PAD_PTA5__I2S0_TX_BCLK 0x0014 0x01C0 0x7 0x1
+#define IMX7ULP_PAD_PTA6__ADC1_CH4A 0x0018 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA6__PTA6 0x0018 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA6__LPSPI0_SCK 0x0018 0x0110 0x3 0x1
+#define IMX7ULP_PAD_PTA6__LPUART1_TX 0x0018 0x020C 0x4 0x1
+#define IMX7ULP_PAD_PTA6__LPI2C1_HREQ 0x0018 0x0184 0x5 0x1
+#define IMX7ULP_PAD_PTA6__TPM0_CH5 0x0018 0x014C 0x6 0x1
+#define IMX7ULP_PAD_PTA6__I2S0_TX_FS 0x0018 0x01C4 0x7 0x1
+#define IMX7ULP_PAD_PTA7__ADC1_CH4B 0x001C 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA7__PTA7 0x001C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA7__LPUART1_RX 0x001C 0x0208 0x4 0x1
+#define IMX7ULP_PAD_PTA7__TPM1_CH1 0x001C 0x0154 0x6 0x1
+#define IMX7ULP_PAD_PTA7__I2S0_TXD0 0x001C 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTA8__ADC1_CH5A 0x0020 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA8__PTA8 0x0020 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA8__LPSPI1_PCS1 0x0020 0x0120 0x3 0x1
+#define IMX7ULP_PAD_PTA8__LPUART2_CTS_B 0x0020 0x0210 0x4 0x1
+#define IMX7ULP_PAD_PTA8__LPI2C2_SCL 0x0020 0x0194 0x5 0x1
+#define IMX7ULP_PAD_PTA8__TPM1_CLKIN 0x0020 0x01AC 0x6 0x1
+#define IMX7ULP_PAD_PTA8__I2S0_TXD1 0x0020 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTA9__ADC1_CH5B 0x0024 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA9__PTA9 0x0024 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA9__LPSPI1_PCS2 0x0024 0x0124 0x3 0x1
+#define IMX7ULP_PAD_PTA9__LPUART2_RTS_B 0x0024 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTA9__LPI2C2_SDA 0x0024 0x0198 0x5 0x1
+#define IMX7ULP_PAD_PTA9__TPM1_CH0 0x0024 0x0150 0x6 0x1
+#define IMX7ULP_PAD_PTA9__NMI0_B 0x0024 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTA10__ADC1_CH6A 0x0028 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA10__PTA10 0x0028 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA10__LPSPI1_PCS3 0x0028 0x0128 0x3 0x1
+#define IMX7ULP_PAD_PTA10__LPUART2_TX 0x0028 0x0218 0x4 0x1
+#define IMX7ULP_PAD_PTA10__LPI2C2_HREQ 0x0028 0x0190 0x5 0x1
+#define IMX7ULP_PAD_PTA10__TPM2_CLKIN 0x0028 0x01F4 0x6 0x1
+#define IMX7ULP_PAD_PTA10__I2S0_RX_BCLK 0x0028 0x01B8 0x7 0x1
+#define IMX7ULP_PAD_PTA11__ADC1_CH6B 0x002C 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA11__PTA11 0x002C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA11__LPUART2_RX 0x002C 0x0214 0x4 0x1
+#define IMX7ULP_PAD_PTA11__TPM2_CH0 0x002C 0x0158 0x6 0x1
+#define IMX7ULP_PAD_PTA11__I2S0_RX_FS 0x002C 0x01BC 0x7 0x2
+#define IMX7ULP_PAD_PTA12__ADC1_CH7A 0x0030 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA12__PTA12 0x0030 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA12__LPSPI1_SIN 0x0030 0x0130 0x3 0x1
+#define IMX7ULP_PAD_PTA12__LPUART3_CTS_B 0x0030 0x021C 0x4 0x1
+#define IMX7ULP_PAD_PTA12__LPI2C3_SCL 0x0030 0x01A0 0x5 0x1
+#define IMX7ULP_PAD_PTA12__TPM2_CH1 0x0030 0x015C 0x6 0x1
+#define IMX7ULP_PAD_PTA12__I2S0_RXD0 0x0030 0x01DC 0x7 0x2
+#define IMX7ULP_PAD_PTA13__ADC1_CH7B 0x0034 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA13__PTA13 0x0034 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA13__LPSPI1_SOUT 0x0034 0x0134 0x3 0x2
+#define IMX7ULP_PAD_PTA13__LPUART3_RTS_B 0x0034 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTA13__LPI2C3_SDA 0x0034 0x01A4 0x5 0x2
+#define IMX7ULP_PAD_PTA13__TPM3_CLKIN 0x0034 0x01B0 0x6 0x1
+#define IMX7ULP_PAD_PTA13__I2S0_RXD1 0x0034 0x01E0 0x7 0x2
+#define IMX7ULP_PAD_PTA13__CMP0_OUT 0x0034 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTA13__LLWU0_P2 0x0034 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTA14__ADC1_CH8A 0x0038 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA14__PTA14 0x0038 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA14__LPSPI1_SCK 0x0038 0x012C 0x3 0x2
+#define IMX7ULP_PAD_PTA14__LPUART3_TX 0x0038 0x0224 0x4 0x2
+#define IMX7ULP_PAD_PTA14__LPI2C3_HREQ 0x0038 0x019C 0x5 0x2
+#define IMX7ULP_PAD_PTA14__TPM3_CH0 0x0038 0x0160 0x6 0x1
+#define IMX7ULP_PAD_PTA14__I2S0_MCLK 0x0038 0x01B4 0x7 0x2
+#define IMX7ULP_PAD_PTA14__LLWU0_P3 0x0038 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTA15__ADC1_CH8B 0x003C 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA15__PTA15 0x003C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA15__LPSPI1_PCS0 0x003C 0x011C 0x3 0x1
+#define IMX7ULP_PAD_PTA15__LPUART3_RX 0x003C 0x0220 0x4 0x1
+#define IMX7ULP_PAD_PTA15__TPM3_CH1 0x003C 0x0164 0x6 0x1
+#define IMX7ULP_PAD_PTA15__I2S0_TX_BCLK 0x003C 0x01C0 0x7 0x2
+#define IMX7ULP_PAD_PTA16__CMP1_IN5_3V 0x0040 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA16__PTA16 0x0040 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA16__FXIO0_D0 0x0040 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA16__LPSPI0_SOUT 0x0040 0x0118 0x3 0x2
+#define IMX7ULP_PAD_PTA16__LPUART0_CTS_B 0x0040 0x01F8 0x4 0x1
+#define IMX7ULP_PAD_PTA16__LPI2C0_SCL 0x0040 0x017C 0x5 0x1
+#define IMX7ULP_PAD_PTA16__TPM3_CH2 0x0040 0x0168 0x6 0x1
+#define IMX7ULP_PAD_PTA16__I2S0_TX_FS 0x0040 0x01C4 0x7 0x2
+#define IMX7ULP_PAD_PTA17__CMP1_IN6_3V 0x0044 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA17__PTA17 0x0044 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA17__FXIO0_D1 0x0044 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA17__LPSPI0_SCK 0x0044 0x0110 0x3 0x2
+#define IMX7ULP_PAD_PTA17__LPUART0_RTS_B 0x0044 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTA17__LPI2C0_SDA 0x0044 0x0180 0x5 0x2
+#define IMX7ULP_PAD_PTA17__TPM3_CH3 0x0044 0x016C 0x6 0x1
+#define IMX7ULP_PAD_PTA17__I2S0_TXD0 0x0044 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTA18__CMP1_IN1_3V 0x0048 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA18__PTA18 0x0048 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA18__FXIO0_D2 0x0048 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA18__LPSPI0_PCS0 0x0048 0x0100 0x3 0x2
+#define IMX7ULP_PAD_PTA18__LPUART0_TX 0x0048 0x0200 0x4 0x2
+#define IMX7ULP_PAD_PTA18__LPI2C0_HREQ 0x0048 0x0178 0x5 0x2
+#define IMX7ULP_PAD_PTA18__TPM3_CH4 0x0048 0x0170 0x6 0x1
+#define IMX7ULP_PAD_PTA18__I2S0_TXD1 0x0048 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTA18__LLWU0_P4 0x0048 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTA19__CMP1_IN3_3V 0x004C 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA19__PTA19 0x004C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA19__FXIO0_D3 0x004C 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA19__LPUART0_RX 0x004C 0x01FC 0x4 0x2
+#define IMX7ULP_PAD_PTA19__TPM3_CH5 0x004C 0x0174 0x6 0x1
+#define IMX7ULP_PAD_PTA19__I2S1_RX_BCLK 0x004C 0x01CC 0x7 0x1
+#define IMX7ULP_PAD_PTA19__LPTMR0_ALT3 0x004C 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTA19__LLWU0_P5 0x004C 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTA20__ADC0_CH10A 0x0050 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA20__PTA20 0x0050 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA20__FXIO0_D4 0x0050 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA20__LPSPI0_SIN 0x0050 0x0114 0x3 0x2
+#define IMX7ULP_PAD_PTA20__LPUART1_CTS_B 0x0050 0x0204 0x4 0x2
+#define IMX7ULP_PAD_PTA20__LPI2C1_SCL 0x0050 0x0188 0x5 0x2
+#define IMX7ULP_PAD_PTA20__TPM0_CLKIN 0x0050 0x01A8 0x6 0x1
+#define IMX7ULP_PAD_PTA20__I2S1_RX_FS 0x0050 0x01D0 0x7 0x1
+#define IMX7ULP_PAD_PTA21__ADC0_CH10B 0x0054 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA21__PTA21 0x0054 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA21__FXIO0_D5 0x0054 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA21__LPSPI0_PCS1 0x0054 0x0104 0x3 0x1
+#define IMX7ULP_PAD_PTA21__LPUART1_RTS_B 0x0054 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTA21__LPI2C1_SDA 0x0054 0x018C 0x5 0x2
+#define IMX7ULP_PAD_PTA21__TPM0_CH0 0x0054 0x0138 0x6 0x2
+#define IMX7ULP_PAD_PTA21__I2S1_RXD0 0x0054 0x01E4 0x7 0x1
+#define IMX7ULP_PAD_PTA22__ADC0_CH9A 0x0058 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA22__PTA22 0x0058 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA22__FXIO0_D6 0x0058 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA22__LPSPI0_PCS2 0x0058 0x0108 0x3 0x2
+#define IMX7ULP_PAD_PTA22__LPUART1_TX 0x0058 0x020C 0x4 0x2
+#define IMX7ULP_PAD_PTA22__LPI2C1_HREQ 0x0058 0x0184 0x5 0x2
+#define IMX7ULP_PAD_PTA22__TPM0_CH1 0x0058 0x013C 0x6 0x2
+#define IMX7ULP_PAD_PTA22__I2S1_RXD1 0x0058 0x01E8 0x7 0x1
+#define IMX7ULP_PAD_PTA22__LPTMR0_ALT2 0x0058 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTA22__EWM_OUT_B 0x0058 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTA23__ADC0_CH9B 0x005C 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA23__PTA23 0x005C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA23__FXIO0_D7 0x005C 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA23__LPSPI0_PCS3 0x005C 0x010C 0x3 0x2
+#define IMX7ULP_PAD_PTA23__LPUART1_RX 0x005C 0x0208 0x4 0x2
+#define IMX7ULP_PAD_PTA23__TPM0_CH2 0x005C 0x0140 0x6 0x2
+#define IMX7ULP_PAD_PTA23__I2S1_MCLK 0x005C 0x01C8 0x7 0x1
+#define IMX7ULP_PAD_PTA23__LLWU0_P6 0x005C 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTA24__ADC0_CH8A 0x0060 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA24__PTA24 0x0060 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA24__FXIO0_D8 0x0060 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA24__LPSPI1_PCS1 0x0060 0x0120 0x3 0x2
+#define IMX7ULP_PAD_PTA24__LPUART2_CTS_B 0x0060 0x0210 0x4 0x2
+#define IMX7ULP_PAD_PTA24__LPI2C2_SCL 0x0060 0x0194 0x5 0x2
+#define IMX7ULP_PAD_PTA24__TPM0_CH3 0x0060 0x0144 0x6 0x2
+#define IMX7ULP_PAD_PTA24__I2S1_TX_BCLK 0x0060 0x01D4 0x7 0x1
+#define IMX7ULP_PAD_PTA25__ADC0_CH8B 0x0064 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA25__PTA25 0x0064 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA25__FXIO0_D9 0x0064 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA25__LPSPI1_PCS2 0x0064 0x0124 0x3 0x2
+#define IMX7ULP_PAD_PTA25__LPUART2_RTS_B 0x0064 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTA25__LPI2C2_SDA 0x0064 0x0198 0x5 0x2
+#define IMX7ULP_PAD_PTA25__TPM0_CH4 0x0064 0x0148 0x6 0x2
+#define IMX7ULP_PAD_PTA25__I2S1_TX_FS 0x0064 0x01D8 0x7 0x1
+#define IMX7ULP_PAD_PTA26__PTA26 0x0068 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA26__JTAG_TMS_SWD_DIO 0x0068 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTA26__FXIO0_D10 0x0068 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA26__LPSPI1_PCS3 0x0068 0x0128 0x3 0x2
+#define IMX7ULP_PAD_PTA26__LPUART2_TX 0x0068 0x0218 0x4 0x2
+#define IMX7ULP_PAD_PTA26__LPI2C2_HREQ 0x0068 0x0190 0x5 0x2
+#define IMX7ULP_PAD_PTA26__TPM0_CH5 0x0068 0x014C 0x6 0x2
+#define IMX7ULP_PAD_PTA26__I2S1_RXD2 0x0068 0x01EC 0x7 0x1
+#define IMX7ULP_PAD_PTA27__PTA27 0x006C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA27__JTAG_TDO 0x006C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTA27__FXIO0_D11 0x006C 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA27__LPUART2_RX 0x006C 0x0214 0x4 0x2
+#define IMX7ULP_PAD_PTA27__TPM1_CH1 0x006C 0x0154 0x6 0x2
+#define IMX7ULP_PAD_PTA27__I2S1_RXD3 0x006C 0x01F0 0x7 0x1
+#define IMX7ULP_PAD_PTA28__PTA28 0x0070 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA28__JTAG_TDI 0x0070 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTA28__FXIO0_D12 0x0070 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA28__LPSPI1_SIN 0x0070 0x0130 0x3 0x2
+#define IMX7ULP_PAD_PTA28__LPUART3_CTS_B 0x0070 0x021C 0x4 0x2
+#define IMX7ULP_PAD_PTA28__LPI2C3_SCL 0x0070 0x01A0 0x5 0x2
+#define IMX7ULP_PAD_PTA28__TPM1_CLKIN 0x0070 0x01AC 0x6 0x2
+#define IMX7ULP_PAD_PTA28__I2S1_TXD2 0x0070 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTA29__PTA29 0x0074 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA29__JTAG_TCLK_SWD_CLK 0x0074 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTA29__FXIO0_D13 0x0074 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA29__LPSPI1_SOUT 0x0074 0x0134 0x3 0x1
+#define IMX7ULP_PAD_PTA29__LPUART3_RTS_B 0x0074 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTA29__LPI2C3_SDA 0x0074 0x01A4 0x5 0x1
+#define IMX7ULP_PAD_PTA29__TPM1_CH0 0x0074 0x0150 0x6 0x2
+#define IMX7ULP_PAD_PTA29__I2S1_TXD3 0x0074 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTA30__ADC0_CH1A 0x0078 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA30__PTA30 0x0078 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA30__FXIO0_D14 0x0078 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA30__LPSPI1_SCK 0x0078 0x012C 0x3 0x1
+#define IMX7ULP_PAD_PTA30__LPUART3_TX 0x0078 0x0224 0x4 0x1
+#define IMX7ULP_PAD_PTA30__LPI2C3_HREQ 0x0078 0x019C 0x5 0x1
+#define IMX7ULP_PAD_PTA30__TPM2_CLKIN 0x0078 0x01F4 0x6 0x2
+#define IMX7ULP_PAD_PTA30__I2S1_TXD0 0x0078 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTA30__JTAG_TRST_B 0x0078 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTA31__ADC0_CH1B 0x007C 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA31__PTA31 0x007C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA31__FXIO0_D15 0x007C 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA31__LPSPI1_PCS0 0x007C 0x011C 0x3 0x2
+#define IMX7ULP_PAD_PTA31__LPUART3_RX 0x007C 0x0220 0x4 0x2
+#define IMX7ULP_PAD_PTA31__TPM2_CH0 0x007C 0x0158 0x6 0x2
+#define IMX7ULP_PAD_PTA31__I2S1_TXD1 0x007C 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTA31__LPTMR0_ALT1 0x007C 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTA31__EWM_IN 0x007C 0x0228 0xc 0x1
+#define IMX7ULP_PAD_PTA31__LLWU0_P7 0x007C 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTB0__ADC0_CH0A 0x0080 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB0__PTB0 0x0080 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB0__FXIO0_D16 0x0080 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB0__LPSPI0_SIN 0x0080 0x0114 0x3 0x3
+#define IMX7ULP_PAD_PTB0__LPUART0_TX 0x0080 0x0200 0x4 0x3
+#define IMX7ULP_PAD_PTB0__TPM2_CH1 0x0080 0x015C 0x6 0x2
+#define IMX7ULP_PAD_PTB0__CLKOUT0 0x0080 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTB0__CMP1_OUT 0x0080 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTB0__EWM_OUT_B 0x0080 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTB1__ADC0_CH0B 0x0084 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB1__PTB1 0x0084 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB1__FXIO0_D17 0x0084 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB1__LPSPI0_SOUT 0x0084 0x0118 0x3 0x3
+#define IMX7ULP_PAD_PTB1__LPUART0_RX 0x0084 0x01FC 0x4 0x3
+#define IMX7ULP_PAD_PTB1__TPM3_CLKIN 0x0084 0x01B0 0x6 0x3
+#define IMX7ULP_PAD_PTB1__I2S1_TX_BCLK 0x0084 0x01D4 0x7 0x2
+#define IMX7ULP_PAD_PTB1__RTC_CLKOUT 0x0084 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTB1__EWM_IN 0x0084 0x0228 0xc 0x2
+#define IMX7ULP_PAD_PTB1__LLWU0_P8 0x0084 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTB2__ADC0_CH6A 0x0088 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB2__PTB2 0x0088 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB2__FXIO0_D18 0x0088 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB2__LPSPI0_SCK 0x0088 0x0110 0x3 0x3
+#define IMX7ULP_PAD_PTB2__LPUART1_TX 0x0088 0x020C 0x4 0x3
+#define IMX7ULP_PAD_PTB2__TPM3_CH0 0x0088 0x0160 0x6 0x2
+#define IMX7ULP_PAD_PTB2__I2S1_TX_FS 0x0088 0x01D8 0x7 0x2
+#define IMX7ULP_PAD_PTB2__TRACE_CLKOUT 0x0088 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTB3__ADC0_CH6B 0x008C 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB3__PTB3 0x008C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB3__FXIO0_D19 0x008C 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB3__LPSPI0_PCS0 0x008C 0x0100 0x3 0x3
+#define IMX7ULP_PAD_PTB3__LPUART1_RX 0x008C 0x0208 0x4 0x3
+#define IMX7ULP_PAD_PTB3__TPM3_CH1 0x008C 0x0164 0x6 0x2
+#define IMX7ULP_PAD_PTB3__I2S1_TXD0 0x008C 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTB3__TRACE_D0 0x008C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTB3__LPTMR1_ALT2 0x008C 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTB3__LLWU0_P9 0x008C 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTB4__PTB4 0x0090 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB4__FXIO0_D20 0x0090 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB4__LPSPI0_PCS1 0x0090 0x0104 0x3 0x3
+#define IMX7ULP_PAD_PTB4__LPUART2_TX 0x0090 0x0218 0x4 0x3
+#define IMX7ULP_PAD_PTB4__LPI2C0_HREQ 0x0090 0x0178 0x5 0x3
+#define IMX7ULP_PAD_PTB4__TPM3_CH2 0x0090 0x0168 0x6 0x2
+#define IMX7ULP_PAD_PTB4__I2S1_TXD1 0x0090 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTB4__QSPIA_DATA7 0x0090 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB4__TRACE_D1 0x0090 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTB4__SEC_VIO_B 0x0090 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTB5__PTB5 0x0094 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB5__FXIO0_D21 0x0094 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB5__LPSPI0_PCS2 0x0094 0x0108 0x3 0x3
+#define IMX7ULP_PAD_PTB5__LPUART2_RX 0x0094 0x0214 0x4 0x3
+#define IMX7ULP_PAD_PTB5__LPI2C1_HREQ 0x0094 0x0184 0x5 0x3
+#define IMX7ULP_PAD_PTB5__TPM3_CH3 0x0094 0x016C 0x6 0x2
+#define IMX7ULP_PAD_PTB5__I2S1_TXD2 0x0094 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTB5__QSPIA_DATA6 0x0094 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB5__TRACE_D2 0x0094 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTB5__RTC_CLKOUT 0x0094 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTB6__ADC1_CH1A 0x0098 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB6__PTB6 0x0098 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB6__FXIO0_D22 0x0098 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB6__LPSPI0_PCS3 0x0098 0x010C 0x3 0x3
+#define IMX7ULP_PAD_PTB6__LPUART3_TX 0x0098 0x0224 0x4 0x3
+#define IMX7ULP_PAD_PTB6__LPI2C0_SCL 0x0098 0x017C 0x5 0x3
+#define IMX7ULP_PAD_PTB6__TPM3_CH4 0x0098 0x0170 0x6 0x2
+#define IMX7ULP_PAD_PTB6__I2S1_TXD3 0x0098 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTB6__QSPIA_DATA5 0x0098 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB6__TRACE_D3 0x0098 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTB6__LPTMR1_ALT3 0x0098 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTB6__LLWU0_P10 0x0098 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTB7__ADC1_CH1B 0x009C 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB7__PTB7 0x009C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB7__FXIO0_D23 0x009C 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB7__LPSPI1_SIN 0x009C 0x0130 0x3 0x3
+#define IMX7ULP_PAD_PTB7__LPUART3_RX 0x009C 0x0220 0x4 0x3
+#define IMX7ULP_PAD_PTB7__LPI2C0_SDA 0x009C 0x0180 0x5 0x3
+#define IMX7ULP_PAD_PTB7__TPM3_CH5 0x009C 0x0174 0x6 0x2
+#define IMX7ULP_PAD_PTB7__I2S1_MCLK 0x009C 0x01C8 0x7 0x2
+#define IMX7ULP_PAD_PTB7__QSPIA_SS1_B 0x009C 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB7__CMP1_OUT 0x009C 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTB7__LLWU0_P11 0x009C 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTB8__ADC0_CH14A_CMP0_IN0 0x00A0 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB8__PTB8 0x00A0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB8__FXIO0_D24 0x00A0 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB8__LPSPI1_SOUT 0x00A0 0x0134 0x3 0x3
+#define IMX7ULP_PAD_PTB8__LPI2C1_SCL 0x00A0 0x0188 0x5 0x3
+#define IMX7ULP_PAD_PTB8__TPM0_CLKIN 0x00A0 0x01A8 0x6 0x3
+#define IMX7ULP_PAD_PTB8__I2S1_RX_BCLK 0x00A0 0x01CC 0x7 0x2
+#define IMX7ULP_PAD_PTB8__QSPIA_SS0_B 0x00A0 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB8__RTC_CLKOUT 0x00A0 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTB9__ADC0_CH14B_CMP0_IN2 0x00A4 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB9__PTB9 0x00A4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB9__FXIO0_D25 0x00A4 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB9__LPSPI1_SCK 0x00A4 0x012C 0x3 0x3
+#define IMX7ULP_PAD_PTB9__LPI2C1_SDA 0x00A4 0x018C 0x5 0x3
+#define IMX7ULP_PAD_PTB9__TPM0_CH0 0x00A4 0x0138 0x6 0x3
+#define IMX7ULP_PAD_PTB9__I2S1_RX_FS 0x00A4 0x01D0 0x7 0x2
+#define IMX7ULP_PAD_PTB9__QSPIA_DQS 0x00A4 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB9__LLWU0_P12 0x00A4 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTB10__CMP0_IN1 0x00A8 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB10__PTB10 0x00A8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB10__FXIO0_D26 0x00A8 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB10__LPSPI1_PCS0 0x00A8 0x011C 0x3 0x3
+#define IMX7ULP_PAD_PTB10__LPI2C2_SCL 0x00A8 0x0194 0x5 0x3
+#define IMX7ULP_PAD_PTB10__TPM0_CH1 0x00A8 0x013C 0x6 0x3
+#define IMX7ULP_PAD_PTB10__I2S1_RXD0 0x00A8 0x01E4 0x7 0x2
+#define IMX7ULP_PAD_PTB10__TRACE_D4 0x00A8 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTB11__CMP0_IN3 0x00AC 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB11__PTB11 0x00AC 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB11__FXIO0_D27 0x00AC 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB11__LPSPI1_PCS1 0x00AC 0x0120 0x3 0x3
+#define IMX7ULP_PAD_PTB11__LPI2C2_SDA 0x00AC 0x0198 0x5 0x3
+#define IMX7ULP_PAD_PTB11__TPM1_CLKIN 0x00AC 0x01AC 0x6 0x3
+#define IMX7ULP_PAD_PTB11__I2S1_RXD1 0x00AC 0x01E8 0x7 0x2
+#define IMX7ULP_PAD_PTB11__TRACE_D5 0x00AC 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTB12__ADC1_CH13A_CMP1_IN0 0x00B0 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB12__PTB12 0x00B0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB12__FXIO0_D28 0x00B0 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB12__LPSPI1_PCS2 0x00B0 0x0124 0x3 0x3
+#define IMX7ULP_PAD_PTB12__LPUART2_TX 0x00B0 0x0218 0x4 0x4
+#define IMX7ULP_PAD_PTB12__LPI2C3_SCL 0x00B0 0x01A0 0x5 0x3
+#define IMX7ULP_PAD_PTB12__TPM1_CH0 0x00B0 0x0150 0x6 0x3
+#define IMX7ULP_PAD_PTB12__I2S1_RXD2 0x00B0 0x01EC 0x7 0x2
+#define IMX7ULP_PAD_PTB12__TRACE_D6 0x00B0 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTB13__ADC1_CH13B_CMP1_IN1 0x00B4 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB13__PTB13 0x00B4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB13__FXIO0_D29 0x00B4 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB13__LPSPI1_PCS3 0x00B4 0x0128 0x3 0x3
+#define IMX7ULP_PAD_PTB13__LPUART2_RX 0x00B4 0x0214 0x4 0x4
+#define IMX7ULP_PAD_PTB13__LPI2C3_SDA 0x00B4 0x01A4 0x5 0x3
+#define IMX7ULP_PAD_PTB13__TPM1_CH1 0x00B4 0x0154 0x6 0x3
+#define IMX7ULP_PAD_PTB13__I2S1_RXD3 0x00B4 0x01F0 0x7 0x2
+#define IMX7ULP_PAD_PTB13__QSPIA_DATA4 0x00B4 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB13__TRACE_D7 0x00B4 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTB14__ADC1_CH2A 0x00B8 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB14__PTB14 0x00B8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB14__FXIO0_D30 0x00B8 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB14__LPI2C2_HREQ 0x00B8 0x0190 0x5 0x3
+#define IMX7ULP_PAD_PTB14__TPM2_CLKIN 0x00B8 0x01F4 0x6 0x3
+#define IMX7ULP_PAD_PTB14__QSPIA_SS1_B 0x00B8 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB14__QSPIA_SCLK_B 0x00B8 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTB14__RTC_CLKOUT 0x00B8 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTB14__LLWU0_P13 0x00B8 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTB15__ADC1_CH2B 0x00BC 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB15__PTB15 0x00BC 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB15__FXIO0_D31 0x00BC 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB15__LPI2C3_HREQ 0x00BC 0x019C 0x5 0x3
+#define IMX7ULP_PAD_PTB15__TPM2_CH0 0x00BC 0x0158 0x6 0x3
+#define IMX7ULP_PAD_PTB15__QSPIA_SCLK 0x00BC 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB16__ADC0_CH4A 0x00C0 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB16__PTB16 0x00C0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB16__TPM2_CH1 0x00C0 0x015C 0x6 0x3
+#define IMX7ULP_PAD_PTB16__QSPIA_DATA3 0x00C0 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB16__LLWU0_P14 0x00C0 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTB17__ADC0_CH4B 0x00C4 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB17__PTB17 0x00C4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB17__TPM3_CLKIN 0x00C4 0x01B0 0x6 0x2
+#define IMX7ULP_PAD_PTB17__QSPIA_DATA2 0x00C4 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB18__ADC0_CH5A 0x00C8 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB18__PTB18 0x00C8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB18__TPM3_CH0 0x00C8 0x0160 0x6 0x3
+#define IMX7ULP_PAD_PTB18__QSPIA_DATA1 0x00C8 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB19__ADC0_CH5B 0x00CC 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB19__PTB19 0x00CC 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB19__TPM3_CH1 0x00CC 0x0164 0x6 0x3
+#define IMX7ULP_PAD_PTB19__QSPIA_DATA0 0x00CC 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB19__USB0_ID 0x00CC 0x0338 0xa 0x0
+#define IMX7ULP_PAD_PTB19__LLWU0_P15 0x00CC 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
+#define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
+#define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
+#define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027C 0x5 0x1
+#define IMX7ULP_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1
+#define IMX7ULP_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC2__LPUART4_TX 0x0008 0x024C 0x4 0x1
+#define IMX7ULP_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1
+#define IMX7ULP_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1
+#define IMX7ULP_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC3__PTC3 0x000C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC3__LPUART4_RX 0x000C 0x0248 0x4 0x1
+#define IMX7ULP_PAD_PTC3__TPM4_CH2 0x000C 0x0288 0x6 0x1
+#define IMX7ULP_PAD_PTC3__FB_AD3 0x000C 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC3__TRACE_D12 0x000C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1
+#define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02A0 0x3 0x1
+#define IMX7ULP_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1
+#define IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x0010 0x02BC 0x5 0x1
+#define IMX7ULP_PAD_PTC4__TPM4_CH3 0x0010 0x028C 0x6 0x1
+#define IMX7ULP_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1
+#define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02A4 0x3 0x1
+#define IMX7ULP_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x0014 0x02C0 0x5 0x1
+#define IMX7ULP_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1
+#define IMX7ULP_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC6__FXIO1_D2 0x0018 0x020C 0x2 0x1
+#define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02A8 0x3 0x1
+#define IMX7ULP_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1
+#define IMX7ULP_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02B8 0x5 0x1
+#define IMX7ULP_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1
+#define IMX7ULP_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC7__PTC7 0x001C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC7__FXIO1_D3 0x001C 0x0210 0x2 0x1
+#define IMX7ULP_PAD_PTC7__LPUART5_RX 0x001C 0x0254 0x4 0x1
+#define IMX7ULP_PAD_PTC7__TPM5_CH1 0x001C 0x02C8 0x6 0x1
+#define IMX7ULP_PAD_PTC7__FB_AD7 0x001C 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC7__TRACE_D8 0x001C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1
+#define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02B0 0x3 0x1
+#define IMX7ULP_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025C 0x4 0x1
+#define IMX7ULP_PAD_PTC8__LPI2C6_SCL 0x0020 0x02FC 0x5 0x1
+#define IMX7ULP_PAD_PTC8__TPM5_CLKIN 0x0020 0x02CC 0x6 0x1
+#define IMX7ULP_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1
+#define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02B4 0x3 0x1
+#define IMX7ULP_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1
+#define IMX7ULP_PAD_PTC9__TPM5_CH0 0x0024 0x02C4 0x6 0x1
+#define IMX7ULP_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC10__FXIO1_D6 0x0028 0x021C 0x2 0x1
+#define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02AC 0x3 0x1
+#define IMX7ULP_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1
+#define IMX7ULP_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02F8 0x5 0x1
+#define IMX7ULP_PAD_PTC10__TPM7_CH3 0x0028 0x02E8 0x6 0x1
+#define IMX7ULP_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC11__PTC11 0x002C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC11__FXIO1_D7 0x002C 0x0220 0x2 0x1
+#define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002C 0x029C 0x3 0x1
+#define IMX7ULP_PAD_PTC11__LPUART6_RX 0x002C 0x0260 0x4 0x1
+#define IMX7ULP_PAD_PTC11__TPM7_CH4 0x002C 0x02EC 0x6 0x1
+#define IMX7ULP_PAD_PTC11__FB_AD11 0x002C 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC11__TRACE_D4 0x002C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1
+#define IMX7ULP_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1
+#define IMX7ULP_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1
+#define IMX7ULP_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1
+#define IMX7ULP_PAD_PTC12__TPM7_CH5 0x0030 0x02F0 0x6 0x1
+#define IMX7ULP_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1
+#define IMX7ULP_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1
+#define IMX7ULP_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTC13__LPI2C7_SDA 0x0034 0x030C 0x5 0x1
+#define IMX7ULP_PAD_PTC13__TPM7_CLKIN 0x0034 0x02F4 0x6 0x1
+#define IMX7ULP_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC13__USB0_ID 0x0034 0x0338 0xb 0x1
+#define IMX7ULP_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC14__FXIO1_D10 0x0038 0x022C 0x2 0x1
+#define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031C 0x3 0x1
+#define IMX7ULP_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1
+#define IMX7ULP_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1
+#define IMX7ULP_PAD_PTC14__TPM7_CH0 0x0038 0x02DC 0x6 0x1
+#define IMX7ULP_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC15__PTC15 0x003C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC15__FXIO1_D11 0x003C 0x0230 0x2 0x1
+#define IMX7ULP_PAD_PTC15__LPUART7_RX 0x003C 0x026C 0x4 0x1
+#define IMX7ULP_PAD_PTC15__TPM7_CH1 0x003C 0x02E0 0x6 0x1
+#define IMX7ULP_PAD_PTC15__FB_AD15 0x003C 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC15__TRACE_D0 0x003C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1
+#define IMX7ULP_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1
+#define IMX7ULP_PAD_PTC16__TPM7_CH2 0x0040 0x02E4 0x6 0x1
+#define IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC16__USB1_OC2 0x0040 0x0334 0xb 0x1
+#define IMX7ULP_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1
+#define IMX7ULP_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1
+#define IMX7ULP_PAD_PTC17__TPM6_CLKIN 0x0044 0x02D8 0x6 0x1
+#define IMX7ULP_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC18__FXIO1_D14 0x0048 0x023C 0x2 0x1
+#define IMX7ULP_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1
+#define IMX7ULP_PAD_PTC18__TPM6_CH0 0x0048 0x02D0 0x6 0x1
+#define IMX7ULP_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC18__USB0_ID 0x0048 0x0338 0xb 0x2
+#define IMX7ULP_PAD_PTC18__VIU_DE 0x0048 0x033C 0xc 0x1
+#define IMX7ULP_PAD_PTC19__PTC19 0x004C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC19__FXIO1_D15 0x004C 0x0240 0x2 0x1
+#define IMX7ULP_PAD_PTC19__LPSPI3_PCS0 0x004C 0x0310 0x3 0x1
+#define IMX7ULP_PAD_PTC19__TPM6_CH1 0x004C 0x02D4 0x6 0x1
+#define IMX7ULP_PAD_PTC19__FB_A16 0x004C 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC19__USB0_ID 0x004C 0x0338 0xa 0x3
+#define IMX7ULP_PAD_PTC19__USB1_PWR2 0x004C 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTC19__VIU_DE 0x004C 0x033C 0xc 0x3
+#define IMX7ULP_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD3__PTD3 0x008C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD3__SDHC0_D7 0x008C 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD7__PTD7 0x009C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD7__SDHC0_D3 0x009C 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD8__PTD8 0x00A0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD8__TPM4_CLKIN 0x00A0 0x0298 0x6 0x2
+#define IMX7ULP_PAD_PTD8__SDHC0_D2 0x00A0 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD9__PTD9 0x00A4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD9__TPM4_CH0 0x00A4 0x0280 0x6 0x2
+#define IMX7ULP_PAD_PTD9__SDHC0_D1 0x00A4 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD10__PTD10 0x00A8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD10__TPM4_CH1 0x00A8 0x0284 0x6 0x2
+#define IMX7ULP_PAD_PTD10__SDHC0_D0 0x00A8 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD11__PTD11 0x00AC 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD11__TPM4_CH2 0x00AC 0x0288 0x6 0x2
+#define IMX7ULP_PAD_PTD11__SDHC0_DQS 0x00AC 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02A0 0x3 0x2
+#define IMX7ULP_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2
+#define IMX7ULP_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2
+#define IMX7ULP_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02A4 0x3 0x2
+#define IMX7ULP_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTE1__LPI2C4_SDA 0x0104 0x027C 0x5 0x2
+#define IMX7ULP_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02A8 0x3 0x2
+#define IMX7ULP_PAD_PTE2__LPUART4_TX 0x0108 0x024C 0x4 0x2
+#define IMX7ULP_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2
+#define IMX7ULP_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE3__PTE3 0x010C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE3__FXIO1_D28 0x010C 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE3__LPUART4_RX 0x010C 0x0248 0x4 0x2
+#define IMX7ULP_PAD_PTE3__TPM5_CH1 0x010C 0x02C8 0x6 0x2
+#define IMX7ULP_PAD_PTE3__SDHC1_CMD 0x010C 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE4__LPSPI2_SIN 0x0110 0x02B0 0x3 0x2
+#define IMX7ULP_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2
+#define IMX7ULP_PAD_PTE4__LPI2C5_SCL 0x0110 0x02BC 0x5 0x2
+#define IMX7ULP_PAD_PTE4__TPM5_CLKIN 0x0110 0x02CC 0x6 0x2
+#define IMX7ULP_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02B4 0x3 0x2
+#define IMX7ULP_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTE5__LPI2C5_SDA 0x0114 0x02C0 0x5 0x2
+#define IMX7ULP_PAD_PTE5__TPM5_CH0 0x0114 0x02C4 0x6 0x2
+#define IMX7ULP_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE5__VIU_DE 0x0114 0x033C 0xc 0x2
+#define IMX7ULP_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE6__LPSPI2_SCK 0x0118 0x02AC 0x3 0x2
+#define IMX7ULP_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2
+#define IMX7ULP_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02B8 0x5 0x2
+#define IMX7ULP_PAD_PTE6__TPM7_CH3 0x0118 0x02E8 0x6 0x2
+#define IMX7ULP_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE6__USB0_OC 0x0118 0x0330 0xb 0x1
+#define IMX7ULP_PAD_PTE7__PTE7 0x011C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE7__FXIO1_D24 0x011C 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE7__LPSPI2_PCS0 0x011C 0x029C 0x3 0x2
+#define IMX7ULP_PAD_PTE7__LPUART5_RX 0x011C 0x0254 0x4 0x2
+#define IMX7ULP_PAD_PTE7__TPM7_CH4 0x011C 0x02EC 0x6 0x2
+#define IMX7ULP_PAD_PTE7__SDHC1_D5 0x011C 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE7__FB_A18 0x011C 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE7__TRACE_D7 0x011C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE7__USB0_PWR 0x011C 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTE7__VIU_FID 0x011C 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2
+#define IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025C 0x4 0x2
+#define IMX7ULP_PAD_PTE8__LPI2C6_SCL 0x0120 0x02FC 0x5 0x2
+#define IMX7ULP_PAD_PTE8__TPM7_CH5 0x0120 0x02F0 0x6 0x2
+#define IMX7ULP_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1
+#define IMX7ULP_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE9__PTE9 0x0124 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE9__TRACE_D5 0x0124 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE9__VIU_D17 0x0124 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE9__FXIO1_D22 0x0124 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2
+#define IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2
+#define IMX7ULP_PAD_PTE9__TPM7_CLKIN 0x0124 0x02F4 0x6 0x2
+#define IMX7ULP_PAD_PTE9__SDHC1_CD 0x0124 0x032C 0x7 0x1
+#define IMX7ULP_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031C 0x3 0x2
+#define IMX7ULP_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2
+#define IMX7ULP_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02F8 0x5 0x2
+#define IMX7ULP_PAD_PTE10__TPM7_CH0 0x0128 0x02DC 0x6 0x2
+#define IMX7ULP_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE11__PTE11 0x012C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE11__TRACE_D3 0x012C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE11__VIU_D19 0x012C 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE11__FXIO1_D20 0x012C 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE11__LPUART6_RX 0x012C 0x0260 0x4 0x2
+#define IMX7ULP_PAD_PTE11__TPM7_CH1 0x012C 0x02E0 0x6 0x2
+#define IMX7ULP_PAD_PTE11__SDHC1_RESET_B 0x012C 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE11__FB_A20 0x012C 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2
+#define IMX7ULP_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2
+#define IMX7ULP_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2
+#define IMX7ULP_PAD_PTE12__TPM7_CH2 0x0130 0x02E4 0x6 0x2
+#define IMX7ULP_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2
+#define IMX7ULP_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE12__USB1_OC2 0x0130 0x0334 0xb 0x2
+#define IMX7ULP_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2
+#define IMX7ULP_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTE13__LPI2C7_SDA 0x0134 0x030C 0x5 0x2
+#define IMX7ULP_PAD_PTE13__TPM6_CLKIN 0x0134 0x02D8 0x6 0x2
+#define IMX7ULP_PAD_PTE13__SDHC1_CD 0x0134 0x032C 0x8 0x2
+#define IMX7ULP_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE13__USB1_PWR2 0x0134 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2
+#define IMX7ULP_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2
+#define IMX7ULP_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2
+#define IMX7ULP_PAD_PTE14__TPM6_CH0 0x0138 0x02D0 0x6 0x2
+#define IMX7ULP_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE14__USB0_OC 0x0138 0x0330 0xb 0x2
+#define IMX7ULP_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE15__PTE15 0x013C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE15__FXIO1_D16 0x013C 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE15__LPSPI3_PCS0 0x013C 0x0310 0x3 0x2
+#define IMX7ULP_PAD_PTE15__LPUART7_RX 0x013C 0x026C 0x4 0x2
+#define IMX7ULP_PAD_PTE15__TPM6_CH1 0x013C 0x02D4 0x6 0x2
+#define IMX7ULP_PAD_PTE15__FB_A24 0x013C 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE15__TRACE_CLKOUT 0x013C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE15__USB0_PWR 0x013C 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTE15__VIU_D23 0x013C 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3
+#define IMX7ULP_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3
+#define IMX7ULP_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3
+#define IMX7ULP_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF0__VIU_DE 0x0180 0x033C 0xc 0x0
+#define IMX7ULP_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTF1__LPI2C4_SDA 0x0184 0x027C 0x5 0x3
+#define IMX7ULP_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3
+#define IMX7ULP_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF2__LPUART4_TX 0x0188 0x024C 0x4 0x3
+#define IMX7ULP_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3
+#define IMX7ULP_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3
+#define IMX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF3__PTF3 0x018C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF3__LPUART4_RX 0x018C 0x0248 0x4 0x3
+#define IMX7ULP_PAD_PTF3__TPM4_CH2 0x018C 0x0288 0x6 0x3
+#define IMX7ULP_PAD_PTF3__FB_AD16 0x018C 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF3__VIU_PCLK 0x018C 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2
+#define IMX7ULP_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02A0 0x3 0x3
+#define IMX7ULP_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3
+#define IMX7ULP_PAD_PTF4__LPI2C5_SCL 0x0190 0x02BC 0x5 0x3
+#define IMX7ULP_PAD_PTF4__TPM4_CH3 0x0190 0x028C 0x6 0x2
+#define IMX7ULP_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2
+#define IMX7ULP_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02A4 0x3 0x3
+#define IMX7ULP_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTF5__LPI2C5_SDA 0x0194 0x02C0 0x5 0x3
+#define IMX7ULP_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2
+#define IMX7ULP_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF6__FXIO1_D2 0x0198 0x020C 0x2 0x2
+#define IMX7ULP_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02A8 0x3 0x3
+#define IMX7ULP_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3
+#define IMX7ULP_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02B8 0x5 0x3
+#define IMX7ULP_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2
+#define IMX7ULP_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF7__PTF7 0x019C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF7__FXIO1_D3 0x019C 0x0210 0x2 0x2
+#define IMX7ULP_PAD_PTF7__LPUART5_RX 0x019C 0x0254 0x4 0x3
+#define IMX7ULP_PAD_PTF7__TPM5_CH1 0x019C 0x02C8 0x6 0x3
+#define IMX7ULP_PAD_PTF7__FB_AD20 0x019C 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF7__VIU_D3 0x019C 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF8__PTF8 0x01A0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF8__FXIO1_D4 0x01A0 0x0214 0x2 0x2
+#define IMX7ULP_PAD_PTF8__LPSPI2_SIN 0x01A0 0x02B0 0x3 0x3
+#define IMX7ULP_PAD_PTF8__LPUART6_CTS_B 0x01A0 0x025C 0x4 0x3
+#define IMX7ULP_PAD_PTF8__LPI2C6_SCL 0x01A0 0x02FC 0x5 0x3
+#define IMX7ULP_PAD_PTF8__TPM5_CLKIN 0x01A0 0x02CC 0x6 0x3
+#define IMX7ULP_PAD_PTF8__FB_AD21 0x01A0 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF8__USB1_CLK 0x01A0 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF8__VIU_D4 0x01A0 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF9__PTF9 0x01A4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF9__FXIO1_D5 0x01A4 0x0218 0x2 0x2
+#define IMX7ULP_PAD_PTF9__LPSPI2_SOUT 0x01A4 0x02B4 0x3 0x3
+#define IMX7ULP_PAD_PTF9__LPUART6_RTS_B 0x01A4 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTF9__LPI2C6_SDA 0x01A4 0x0300 0x5 0x3
+#define IMX7ULP_PAD_PTF9__TPM5_CH0 0x01A4 0x02C4 0x6 0x3
+#define IMX7ULP_PAD_PTF9__FB_AD22 0x01A4 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF9__USB1_NXT 0x01A4 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF9__VIU_D5 0x01A4 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF10__PTF10 0x01A8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF10__FXIO1_D6 0x01A8 0x021C 0x2 0x2
+#define IMX7ULP_PAD_PTF10__LPSPI2_SCK 0x01A8 0x02AC 0x3 0x3
+#define IMX7ULP_PAD_PTF10__LPUART6_TX 0x01A8 0x0264 0x4 0x3
+#define IMX7ULP_PAD_PTF10__LPI2C6_HREQ 0x01A8 0x02F8 0x5 0x3
+#define IMX7ULP_PAD_PTF10__TPM7_CH3 0x01A8 0x02E8 0x6 0x3
+#define IMX7ULP_PAD_PTF10__FB_AD23 0x01A8 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF10__USB1_STP 0x01A8 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF10__VIU_D6 0x01A8 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF11__PTF11 0x01AC 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF11__FXIO1_D7 0x01AC 0x0220 0x2 0x2
+#define IMX7ULP_PAD_PTF11__LPSPI2_PCS0 0x01AC 0x029C 0x3 0x3
+#define IMX7ULP_PAD_PTF11__LPUART6_RX 0x01AC 0x0260 0x4 0x3
+#define IMX7ULP_PAD_PTF11__TPM7_CH4 0x01AC 0x02EC 0x6 0x3
+#define IMX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01AC 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF11__USB1_DIR 0x01AC 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF11__VIU_D7 0x01AC 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF12__PTF12 0x01B0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF12__FXIO1_D8 0x01B0 0x0224 0x2 0x2
+#define IMX7ULP_PAD_PTF12__LPSPI3_PCS1 0x01B0 0x0314 0x3 0x3
+#define IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x01B0 0x0268 0x4 0x3
+#define IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x01B0 0x0308 0x5 0x3
+#define IMX7ULP_PAD_PTF12__TPM7_CH5 0x01B0 0x02F0 0x6 0x3
+#define IMX7ULP_PAD_PTF12__FB_AD24 0x01B0 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF12__USB1_DATA0 0x01B0 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF12__VIU_D8 0x01B0 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF13__PTF13 0x01B4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF13__FXIO1_D9 0x01B4 0x0228 0x2 0x2
+#define IMX7ULP_PAD_PTF13__LPSPI3_PCS2 0x01B4 0x0318 0x3 0x3
+#define IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x01B4 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x01B4 0x030C 0x5 0x3
+#define IMX7ULP_PAD_PTF13__TPM7_CLKIN 0x01B4 0x02F4 0x6 0x3
+#define IMX7ULP_PAD_PTF13__FB_AD25 0x01B4 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF13__USB1_DATA1 0x01B4 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF13__VIU_D9 0x01B4 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF14__PTF14 0x01B8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF14__FXIO1_D10 0x01B8 0x022C 0x2 0x2
+#define IMX7ULP_PAD_PTF14__LPSPI3_PCS3 0x01B8 0x031C 0x3 0x3
+#define IMX7ULP_PAD_PTF14__LPUART7_TX 0x01B8 0x0270 0x4 0x3
+#define IMX7ULP_PAD_PTF14__LPI2C7_HREQ 0x01B8 0x0304 0x5 0x3
+#define IMX7ULP_PAD_PTF14__TPM7_CH0 0x01B8 0x02DC 0x6 0x3
+#define IMX7ULP_PAD_PTF14__FB_AD26 0x01B8 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF14__USB1_DATA2 0x01B8 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF14__VIU_D10 0x01B8 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF15__PTF15 0x01BC 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF15__FXIO1_D11 0x01BC 0x0230 0x2 0x2
+#define IMX7ULP_PAD_PTF15__LPUART7_RX 0x01BC 0x026C 0x4 0x3
+#define IMX7ULP_PAD_PTF15__TPM7_CH1 0x01BC 0x02E0 0x6 0x3
+#define IMX7ULP_PAD_PTF15__FB_AD27 0x01BC 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF15__USB1_DATA3 0x01BC 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF15__VIU_D11 0x01BC 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF16__PTF16 0x01C0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF16__USB1_DATA4 0x01C0 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF16__VIU_D12 0x01C0 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF16__FXIO1_D12 0x01C0 0x0234 0x2 0x2
+#define IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x01C0 0x0324 0x3 0x3
+#define IMX7ULP_PAD_PTF16__TPM7_CH2 0x01C0 0x02E4 0x6 0x3
+#define IMX7ULP_PAD_PTF16__FB_AD28 0x01C0 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF17__PTF17 0x01C4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF17__USB1_DATA5 0x01C4 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF17__VIU_D13 0x01C4 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF17__FXIO1_D13 0x01C4 0x0238 0x2 0x2
+#define IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x01C4 0x0328 0x3 0x3
+#define IMX7ULP_PAD_PTF17__TPM6_CLKIN 0x01C4 0x02D8 0x6 0x3
+#define IMX7ULP_PAD_PTF17__FB_AD29 0x01C4 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF18__PTF18 0x01C8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF18__USB1_DATA6 0x01C8 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF18__VIU_D14 0x01C8 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF18__FXIO1_D14 0x01C8 0x023C 0x2 0x2
+#define IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x01C8 0x0320 0x3 0x3
+#define IMX7ULP_PAD_PTF18__TPM6_CH0 0x01C8 0x02D0 0x6 0x3
+#define IMX7ULP_PAD_PTF18__FB_AD30 0x01C8 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF19__PTF19 0x01CC 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF19__USB1_DATA7 0x01CC 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF19__VIU_D15 0x01CC 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF19__FXIO1_D15 0x01CC 0x0240 0x2 0x2
+#define IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x01CC 0x0310 0x3 0x3
+#define IMX7ULP_PAD_PTF19__TPM6_CH1 0x01CC 0x02D4 0x6 0x3
+#define IMX7ULP_PAD_PTF19__FB_AD31 0x01CC 0x0000 0x9 0x0
-#define ULP1_PAD_PTA0_LLWU0_P0__CMP0_IN2A 0x0000 0x0000 0x0 0x0
-#define ULP1_PAD_PTA0_LLWU0_P0__PTA0 0x0000 0x0000 0x1 0x0
-#define ULP1_PAD_PTA0_LLWU0_P0__LLWU0_P0 0x0000 0x0000 0xd 0x0
-#define ULP1_PAD_PTA0_LLWU0_P0__LPSPI0_PCS1 0x0000 0xd104 0x3 0x2
-#define ULP1_PAD_PTA0_LLWU0_P0__LPUART0_CTS_B 0x0000 0xd1f8 0x4 0x2
-#define ULP1_PAD_PTA0_LLWU0_P0__LPI2C0_SCL 0x0000 0xd17c 0x5 0x2
-#define ULP1_PAD_PTA0_LLWU0_P0__TPM0_CLKIN 0x0000 0xd1a8 0x6 0x2
-#define ULP1_PAD_PTA0_LLWU0_P0__I2S0_RX_BCLK 0x0000 0x01b8 0x7 0x2
-#define ULP1_PAD_PTA1__CMP0_IN2B 0x0004 0x0000 0x0 0x0
-#define ULP1_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0
-#define ULP1_PAD_PTA1__LPSPI0_PCS2 0x0004 0xd108 0x3 0x1
-#define ULP1_PAD_PTA1__LPUART0_RTS_B 0x0004 0x0000 0x4 0x0
-#define ULP1_PAD_PTA1__LPI2C0_SDA 0x0004 0xd180 0x5 0x1
-#define ULP1_PAD_PTA1__TPM0_CH0 0x0004 0xd138 0x6 0x1
-#define ULP1_PAD_PTA1__I2S0_RX_FS 0x0004 0x01bc 0x7 0x1
-#define ULP1_PAD_PTA2__CMP1_IN2A 0x0008 0x0000 0x0 0x0
-#define ULP1_PAD_PTA2__PTA2 0x0008 0x0000 0x1 0x0
-#define ULP1_PAD_PTA2__LPSPI0_PCS3 0x0008 0xd10c 0x3 0x1
-#define ULP1_PAD_PTA2__LPUART0_TX 0x0008 0xd200 0x4 0x1
-#define ULP1_PAD_PTA2__LPI2C0_HREQ 0x0008 0xd178 0x5 0x1
-#define ULP1_PAD_PTA2__TPM0_CH1 0x0008 0xd13c 0x6 0x1
-#define ULP1_PAD_PTA2__I2S0_RXD0 0x0008 0x01dc 0x7 0x1
-#define ULP1_PAD_PTA3_LLWU0_P1__CMP1_IN2B 0x000c 0x0000 0x0 0x0
-#define ULP1_PAD_PTA3_LLWU0_P1__PTA3 0x000c 0x0000 0x1 0x0
-#define ULP1_PAD_PTA3_LLWU0_P1__CMP0_OUT 0x000c 0x0000 0xb 0x0
-#define ULP1_PAD_PTA3_LLWU0_P1__LLWU0_P1 0x000c 0x0000 0xd 0x0
-#define ULP1_PAD_PTA3_LLWU0_P1__LPUART0_RX 0x000c 0xd1fc 0x4 0x1
-#define ULP1_PAD_PTA3_LLWU0_P1__TPM0_CH2 0x000c 0xd140 0x6 0x1
-#define ULP1_PAD_PTA3_LLWU0_P1__I2S0_RXD1 0x000c 0x01e0 0x7 0x1
-#define ULP1_PAD_PTA4__ADC1_CH2A 0x0010 0x0000 0x0 0x0
-#define ULP1_PAD_PTA4__PTA4 0x0010 0x0000 0x1 0x0
-#define ULP1_PAD_PTA4__LPSPI0_SIN 0x0010 0xd114 0x3 0x1
-#define ULP1_PAD_PTA4__LPUART1_CTS_B 0x0010 0xd204 0x4 0x1
-#define ULP1_PAD_PTA4__LPI2C1_SCL 0x0010 0xd188 0x5 0x1
-#define ULP1_PAD_PTA4__TPM0_CH3 0x0010 0xd144 0x6 0x1
-#define ULP1_PAD_PTA4__I2S0_MCLK 0x0010 0x01b4 0x7 0x1
-#define ULP1_PAD_PTA5__ADC1_CH2B 0x0014 0x0000 0x0 0x0
-#define ULP1_PAD_PTA5__PTA5 0x0014 0x0000 0x1 0x0
-#define ULP1_PAD_PTA5__LPSPI0_SOUT 0x0014 0xd118 0x3 0x1
-#define ULP1_PAD_PTA5__LPUART1_RTS_B 0x0014 0x0000 0x4 0x0
-#define ULP1_PAD_PTA5__LPI2C1_SDA 0x0014 0xd18c 0x5 0x1
-#define ULP1_PAD_PTA5__TPM0_CH4 0x0014 0xd148 0x6 0x1
-#define ULP1_PAD_PTA5__I2S0_TX_BCLK 0x0014 0x01c0 0x7 0x1
-#define ULP1_PAD_PTA6__ADC1_CH3A 0x0018 0x0000 0x0 0x0
-#define ULP1_PAD_PTA6__PTA6 0x0018 0x0000 0x1 0x0
-#define ULP1_PAD_PTA6__LPSPI0_SCK 0x0018 0xd110 0x3 0x1
-#define ULP1_PAD_PTA6__LPUART1_TX 0x0018 0xd20c 0x4 0x1
-#define ULP1_PAD_PTA6__LPI2C1_HREQ 0x0018 0xd184 0x5 0x1
-#define ULP1_PAD_PTA6__TPM0_CH5 0x0018 0xd14c 0x6 0x1
-#define ULP1_PAD_PTA6__I2S0_TX_FS 0x0018 0x01c4 0x7 0x1
-#define ULP1_PAD_PTA7__ADC1_CH3B 0x001c 0x0000 0x0 0x0
-#define ULP1_PAD_PTA7__PTA7 0x001c 0x0000 0x1 0x0
-#define ULP1_PAD_PTA7__LPSPI0_PCS0 0x001c 0xd100 0x3 0x1
-#define ULP1_PAD_PTA7__LPUART1_RX 0x001c 0xd208 0x4 0x1
-#define ULP1_PAD_PTA7__TPM1_CH1 0x001c 0xd154 0x6 0x1
-#define ULP1_PAD_PTA7__I2S0_TXD0 0x001c 0x0000 0x7 0x0
-#define ULP1_PAD_PTA8__ADC1_CH7A 0x0020 0x0000 0x0 0x0
-#define ULP1_PAD_PTA8__PTA8 0x0020 0x0000 0x1 0x0
-#define ULP1_PAD_PTA8__LPSPI1_PCS1 0x0020 0xd120 0x3 0x1
-#define ULP1_PAD_PTA8__LPUART2_CTS_B 0x0020 0xd210 0x4 0x1
-#define ULP1_PAD_PTA8__LPI2C2_SCL 0x0020 0xd194 0x5 0x1
-#define ULP1_PAD_PTA8__TPM1_CLKIN 0x0020 0xd1ac 0x6 0x1
-#define ULP1_PAD_PTA8__I2S0_TXD1 0x0020 0x0000 0x7 0x0
-#define ULP1_PAD_PTA9__ADC1_CH7B 0x0024 0x0000 0x0 0x0
-#define ULP1_PAD_PTA9__PTA9 0x0024 0x0000 0x1 0x0
-#define ULP1_PAD_PTA9__NMI0_B 0x0024 0x0000 0xb 0x0
-#define ULP1_PAD_PTA9__LPSPI1_PCS2 0x0024 0xd124 0x3 0x1
-#define ULP1_PAD_PTA9__LPUART2_RTS_B 0x0024 0x0000 0x4 0x0
-#define ULP1_PAD_PTA9__LPI2C2_SDA 0x0024 0xd198 0x5 0x1
-#define ULP1_PAD_PTA9__TPM1_CH0 0x0024 0xd150 0x6 0x1
-#define ULP1_PAD_PTA10__ADC1_CH6A 0x0028 0x0000 0x0 0x0
-#define ULP1_PAD_PTA10__PTA10 0x0028 0x0000 0x1 0x0
-#define ULP1_PAD_PTA10__LPSPI1_PCS3 0x0028 0xd128 0x3 0x1
-#define ULP1_PAD_PTA10__LPUART2_TX 0x0028 0xd218 0x4 0x1
-#define ULP1_PAD_PTA10__LPI2C2_HREQ 0x0028 0xd190 0x5 0x1
-#define ULP1_PAD_PTA10__TPM2_CLKIN 0x0028 0xd1f4 0x6 0x1
-#define ULP1_PAD_PTA10__I2S0_RX_BCLK 0x0028 0x01b8 0x7 0x1
-#define ULP1_PAD_PTA11__ADC1_CH6B 0x002c 0x0000 0x0 0x0
-#define ULP1_PAD_PTA11__PTA11 0x002c 0x0000 0x1 0x0
-#define ULP1_PAD_PTA11__LPUART2_RX 0x002c 0xd214 0x4 0x1
-#define ULP1_PAD_PTA11__TPM2_CH0 0x002c 0xd158 0x6 0x1
-#define ULP1_PAD_PTA11__I2S0_RX_FS 0x002c 0x01bc 0x7 0x2
-#define ULP1_PAD_PTA12__ADC1_CH5A 0x0030 0x0000 0x0 0x0
-#define ULP1_PAD_PTA12__PTA12 0x0030 0x0000 0x1 0x0
-#define ULP1_PAD_PTA12__LPSPI1_SIN 0x0030 0xd130 0x3 0x1
-#define ULP1_PAD_PTA12__LPUART3_CTS_B 0x0030 0xd21c 0x4 0x1
-#define ULP1_PAD_PTA12__LPI2C3_SCL 0x0030 0xd1a0 0x5 0x1
-#define ULP1_PAD_PTA12__TPM2_CH1 0x0030 0xd15c 0x6 0x1
-#define ULP1_PAD_PTA12__I2S0_RXD0 0x0030 0x01dc 0x7 0x2
-#define ULP1_PAD_PTA13_LLWU0_P2__ADC1_CH5B 0x0034 0x0000 0x0 0x0
-#define ULP1_PAD_PTA13_LLWU0_P2__PTA13 0x0034 0x0000 0x1 0x0
-#define ULP1_PAD_PTA13_LLWU0_P2__CMP0_OUT 0x0034 0x0000 0xb 0x0
-#define ULP1_PAD_PTA13_LLWU0_P2__LLWU0_P2 0x0034 0x0000 0xd 0x0
-#define ULP1_PAD_PTA13_LLWU0_P2__LPSPI1_SOUT 0x0034 0xd134 0x3 0x2
-#define ULP1_PAD_PTA13_LLWU0_P2__LPUART3_RTS_B 0x0034 0x0000 0x4 0x0
-#define ULP1_PAD_PTA13_LLWU0_P2__LPI2C3_SDA 0x0034 0xd1a4 0x5 0x2
-#define ULP1_PAD_PTA13_LLWU0_P2__TPM3_CLKIN 0x0034 0xd1b0 0x6 0x1
-#define ULP1_PAD_PTA13_LLWU0_P2__I2S0_RXD1 0x0034 0x01e0 0x7 0x2
-#define ULP1_PAD_PTA14_LLWU0_P3__ADC1_CH4A 0x0038 0x0000 0x0 0x0
-#define ULP1_PAD_PTA14_LLWU0_P3__PTA14 0x0038 0x0000 0x1 0x0
-#define ULP1_PAD_PTA14_LLWU0_P3__LLWU0_P3 0x0038 0x0000 0xd 0x0
-#define ULP1_PAD_PTA14_LLWU0_P3__LPSPI1_SCK 0x0038 0xd12c 0x3 0x2
-#define ULP1_PAD_PTA14_LLWU0_P3__LPUART3_TX 0x0038 0xd224 0x4 0x2
-#define ULP1_PAD_PTA14_LLWU0_P3__LPI2C3_HREQ 0x0038 0xd19c 0x5 0x2
-#define ULP1_PAD_PTA14_LLWU0_P3__TPM3_CH0 0x0038 0xd160 0x6 0x1
-#define ULP1_PAD_PTA14_LLWU0_P3__I2S0_MCLK 0x0038 0x01b4 0x7 0x2
-#define ULP1_PAD_PTA15__ADC1_CH4B 0x003c 0x0000 0x0 0x0
-#define ULP1_PAD_PTA15__PTA15 0x003c 0x0000 0x1 0x0
-#define ULP1_PAD_PTA15__LPSPI1_PCS0 0x003c 0xd11c 0x3 0x1
-#define ULP1_PAD_PTA15__LPUART3_RX 0x003c 0xd220 0x4 0x1
-#define ULP1_PAD_PTA15__TPM3_CH1 0x003c 0xd164 0x6 0x1
-#define ULP1_PAD_PTA15__I2S0_TX_BCLK 0x003c 0x01c0 0x7 0x2
-#define ULP1_PAD_PTA16__CMP1_IN0A 0x0040 0x0000 0x0 0x0
-#define ULP1_PAD_PTA16__PTA16 0x0040 0x0000 0x1 0x0
-#define ULP1_PAD_PTA16__FXIO0_D0 0x0040 0x0000 0x2 0x0
-#define ULP1_PAD_PTA16__LPSPI0_PCS1 0x0040 0xd104 0x3 0x1
-#define ULP1_PAD_PTA16__LPUART0_CTS_B 0x0040 0xd1f8 0x4 0x1
-#define ULP1_PAD_PTA16__LPI2C0_SCL 0x0040 0xd17c 0x5 0x1
-#define ULP1_PAD_PTA16__TPM3_CH2 0x0040 0xd168 0x6 0x1
-#define ULP1_PAD_PTA16__I2S0_TX_FS 0x0040 0x01c4 0x7 0x2
-#define ULP1_PAD_PTA17__CMP1_IN0B 0x0044 0x0000 0x0 0x0
-#define ULP1_PAD_PTA17__PTA17 0x0044 0x0000 0x1 0x0
-#define ULP1_PAD_PTA17__FXIO0_D1 0x0044 0x0000 0x2 0x0
-#define ULP1_PAD_PTA17__LPSPI0_PCS2 0x0044 0xd108 0x3 0x2
-#define ULP1_PAD_PTA17__LPUART0_RTS_B 0x0044 0x0000 0x4 0x0
-#define ULP1_PAD_PTA17__LPI2C0_SDA 0x0044 0xd180 0x5 0x2
-#define ULP1_PAD_PTA17__TPM3_CH3 0x0044 0xd16c 0x6 0x1
-#define ULP1_PAD_PTA17__I2S0_TXD0 0x0044 0x0000 0x7 0x0
-#define ULP1_PAD_PTA18_LLWU0_P4__CMP1_IN1A 0x0048 0x0000 0x0 0x0
-#define ULP1_PAD_PTA18_LLWU0_P4__PTA18 0x0048 0x0000 0x1 0x0
-#define ULP1_PAD_PTA18_LLWU0_P4__NMI1_B 0x0048 0x0000 0xb 0x0
-#define ULP1_PAD_PTA18_LLWU0_P4__LLWU0_P4 0x0048 0x0000 0xd 0x0
-#define ULP1_PAD_PTA18_LLWU0_P4__FXIO0_D2 0x0048 0x0000 0x2 0x0
-#define ULP1_PAD_PTA18_LLWU0_P4__LPSPI0_PCS3 0x0048 0xd10c 0x3 0x2
-#define ULP1_PAD_PTA18_LLWU0_P4__LPUART0_TX 0x0048 0xd200 0x4 0x2
-#define ULP1_PAD_PTA18_LLWU0_P4__LPI2C0_HREQ 0x0048 0xd178 0x5 0x2
-#define ULP1_PAD_PTA18_LLWU0_P4__TPM3_CH4 0x0048 0xd170 0x6 0x1
-#define ULP1_PAD_PTA18_LLWU0_P4__I2S0_TXD1 0x0048 0x0000 0x7 0x0
-#define ULP1_PAD_PTA19_LLWU0_P5__CMP1_IN1B 0x004c 0x0000 0x0 0x0
-#define ULP1_PAD_PTA19_LLWU0_P5__PTA19 0x004c 0x0000 0x1 0x0
-#define ULP1_PAD_PTA19_LLWU0_P5__LPTMR0_ALT3 0x004c 0x0000 0xb 0x0
-#define ULP1_PAD_PTA19_LLWU0_P5__LLWU0_P5 0x004c 0x0000 0xd 0x0
-#define ULP1_PAD_PTA19_LLWU0_P5__FXIO0_D3 0x004c 0x0000 0x2 0x0
-#define ULP1_PAD_PTA19_LLWU0_P5__LPUART0_RX 0x004c 0xd1fc 0x4 0x2
-#define ULP1_PAD_PTA19_LLWU0_P5__TPM3_CH5 0x004c 0xd174 0x6 0x1
-#define ULP1_PAD_PTA19_LLWU0_P5__I2S1_RX_BCLK 0x004c 0xd1cc 0x7 0x1
-#define ULP1_PAD_PTA20__ADC0_CH7A 0x0050 0x0000 0x0 0x0
-#define ULP1_PAD_PTA20__PTA20 0x0050 0x0000 0x1 0x0
-#define ULP1_PAD_PTA20__FXIO0_D4 0x0050 0x0000 0x2 0x0
-#define ULP1_PAD_PTA20__LPSPI0_SIN 0x0050 0xd114 0x3 0x2
-#define ULP1_PAD_PTA20__LPUART1_CTS_B 0x0050 0xd204 0x4 0x2
-#define ULP1_PAD_PTA20__LPI2C1_SCL 0x0050 0xd188 0x5 0x2
-#define ULP1_PAD_PTA20__TPM0_CLKIN 0x0050 0xd1a8 0x6 0x1
-#define ULP1_PAD_PTA20__I2S1_RX_FS 0x0050 0xd1d0 0x7 0x1
-#define ULP1_PAD_PTA21__ADC0_CH7B 0x0054 0x0000 0x0 0x0
-#define ULP1_PAD_PTA21__PTA21 0x0054 0x0000 0x1 0x0
-#define ULP1_PAD_PTA21__FXIO0_D5 0x0054 0x0000 0x2 0x0
-#define ULP1_PAD_PTA21__LPSPI0_SOUT 0x0054 0xd118 0x3 0x2
-#define ULP1_PAD_PTA21__LPUART1_RTS_B 0x0054 0x0000 0x4 0x0
-#define ULP1_PAD_PTA21__LPI2C1_SDA 0x0054 0xd18c 0x5 0x2
-#define ULP1_PAD_PTA21__TPM0_CH0 0x0054 0xd138 0x6 0x2
-#define ULP1_PAD_PTA21__I2S1_RXD0 0x0054 0xd1e4 0x7 0x1
-#define ULP1_PAD_PTA22__ADC0_CH6A 0x0058 0x0000 0x0 0x0
-#define ULP1_PAD_PTA22__PTA22 0x0058 0x0000 0x1 0x0
-#define ULP1_PAD_PTA22__LPTMR0_ALT2 0x0058 0x0000 0xb 0x0
-#define ULP1_PAD_PTA22__EWM_OUT_B 0x0058 0x0000 0xc 0x0
-#define ULP1_PAD_PTA22__FXIO0_D6 0x0058 0x0000 0x2 0x0
-#define ULP1_PAD_PTA22__LPSPI0_SCK 0x0058 0xd110 0x3 0x2
-#define ULP1_PAD_PTA22__LPUART1_TX 0x0058 0xd20c 0x4 0x2
-#define ULP1_PAD_PTA22__LPI2C1_HREQ 0x0058 0xd184 0x5 0x2
-#define ULP1_PAD_PTA22__TPM0_CH1 0x0058 0xd13c 0x6 0x2
-#define ULP1_PAD_PTA22__I2S1_RXD1 0x0058 0xd1e8 0x7 0x1
-#define ULP1_PAD_PTA23_LLWU0_P6__ADC0_CH6B 0x005c 0x0000 0x0 0x0
-#define ULP1_PAD_PTA23_LLWU0_P6__PTA23 0x005c 0x0000 0x1 0x0
-#define ULP1_PAD_PTA23_LLWU0_P6__LLWU0_P6 0x005c 0x0000 0xd 0x0
-#define ULP1_PAD_PTA23_LLWU0_P6__FXIO0_D7 0x005c 0x0000 0x2 0x0
-#define ULP1_PAD_PTA23_LLWU0_P6__LPSPI0_PCS0 0x005c 0xd100 0x3 0x2
-#define ULP1_PAD_PTA23_LLWU0_P6__LPUART1_RX 0x005c 0xd208 0x4 0x2
-#define ULP1_PAD_PTA23_LLWU0_P6__TPM0_CH2 0x005c 0xd140 0x6 0x2
-#define ULP1_PAD_PTA23_LLWU0_P6__I2S1_MCLK 0x005c 0xd1c8 0x7 0x1
-#define ULP1_PAD_PTA24__ADC0_CH5A 0x0060 0x0000 0x0 0x0
-#define ULP1_PAD_PTA24__PTA24 0x0060 0x0000 0x1 0x0
-#define ULP1_PAD_PTA24__FXIO0_D8 0x0060 0x0000 0x2 0x0
-#define ULP1_PAD_PTA24__LPSPI1_PCS1 0x0060 0xd120 0x3 0x2
-#define ULP1_PAD_PTA24__LPUART2_CTS_B 0x0060 0xd210 0x4 0x2
-#define ULP1_PAD_PTA24__LPI2C2_SCL 0x0060 0xd194 0x5 0x2
-#define ULP1_PAD_PTA24__TPM0_CH3 0x0060 0xd144 0x6 0x2
-#define ULP1_PAD_PTA24__I2S1_TX_BCLK 0x0060 0xd1d4 0x7 0x1
-#define ULP1_PAD_PTA25__ADC0_CH5B 0x0064 0x0000 0x0 0x0
-#define ULP1_PAD_PTA25__PTA25 0x0064 0x0000 0x1 0x0
-#define ULP1_PAD_PTA25__FXIO0_D9 0x0064 0x0000 0x2 0x0
-#define ULP1_PAD_PTA25__LPSPI1_PCS2 0x0064 0xd124 0x3 0x2
-#define ULP1_PAD_PTA25__LPUART2_RTS_B 0x0064 0x0000 0x4 0x0
-#define ULP1_PAD_PTA25__LPI2C2_SDA 0x0064 0xd198 0x5 0x2
-#define ULP1_PAD_PTA25__TPM0_CH4 0x0064 0xd148 0x6 0x2
-#define ULP1_PAD_PTA25__I2S1_TX_FS 0x0064 0xd1d8 0x7 0x1
-#define ULP1_PAD_PTA26__PTA26 0x0068 0x0000 0x1 0x0
-#define ULP1_PAD_PTA26__JTAG_TMS_SWD_DIO 0x0068 0x0000 0xa 0x0
-#define ULP1_PAD_PTA26__FXIO0_D10 0x0068 0x0000 0x2 0x0
-#define ULP1_PAD_PTA26__LPSPI1_PCS3 0x0068 0xd128 0x3 0x2
-#define ULP1_PAD_PTA26__LPUART2_TX 0x0068 0xd218 0x4 0x2
-#define ULP1_PAD_PTA26__LPI2C2_HREQ 0x0068 0xd190 0x5 0x2
-#define ULP1_PAD_PTA26__TPM0_CH5 0x0068 0xd14c 0x6 0x2
-#define ULP1_PAD_PTA26__I2S1_RXD2 0x0068 0xd1ec 0x7 0x1
-#define ULP1_PAD_PTA27__PTA27 0x006c 0x0000 0x1 0x0
-#define ULP1_PAD_PTA27__JTAG_TDO 0x006c 0x0000 0xa 0x0
-#define ULP1_PAD_PTA27__FXIO0_D11 0x006c 0x0000 0x2 0x0
-#define ULP1_PAD_PTA27__LPUART2_RX 0x006c 0xd214 0x4 0x2
-#define ULP1_PAD_PTA27__TPM1_CH1 0x006c 0xd154 0x6 0x2
-#define ULP1_PAD_PTA27__I2S1_RXD3 0x006c 0xd1f0 0x7 0x1
-#define ULP1_PAD_PTA28__PTA28 0x0070 0x0000 0x1 0x0
-#define ULP1_PAD_PTA28__JTAG_TDI 0x0070 0x0000 0xa 0x0
-#define ULP1_PAD_PTA28__FXIO0_D12 0x0070 0x0000 0x2 0x0
-#define ULP1_PAD_PTA28__LPSPI1_SIN 0x0070 0xd130 0x3 0x2
-#define ULP1_PAD_PTA28__LPUART3_CTS_B 0x0070 0xd21c 0x4 0x2
-#define ULP1_PAD_PTA28__LPI2C3_SCL 0x0070 0xd1a0 0x5 0x2
-#define ULP1_PAD_PTA28__TPM1_CLKIN 0x0070 0xd1ac 0x6 0x2
-#define ULP1_PAD_PTA28__I2S1_TXD2 0x0070 0x0000 0x7 0x0
-#define ULP1_PAD_PTA29__PTA29 0x0074 0x0000 0x1 0x0
-#define ULP1_PAD_PTA29__JTAG_TCLK_SWD_CLK 0x0074 0x0000 0xa 0x0
-#define ULP1_PAD_PTA29__FXIO0_D13 0x0074 0x0000 0x2 0x0
-#define ULP1_PAD_PTA29__LPSPI1_SOUT 0x0074 0xd134 0x3 0x1
-#define ULP1_PAD_PTA29__LPUART3_RTS_B 0x0074 0x0000 0x4 0x0
-#define ULP1_PAD_PTA29__LPI2C3_SDA 0x0074 0xd1a4 0x5 0x1
-#define ULP1_PAD_PTA29__TPM1_CH0 0x0074 0xd150 0x6 0x2
-#define ULP1_PAD_PTA29__I2S1_TXD3 0x0074 0x0000 0x7 0x0
-#define ULP1_PAD_PTA30__ADC0_CH4A 0x0078 0x0000 0x0 0x0
-#define ULP1_PAD_PTA30__PTA30 0x0078 0x0000 0x1 0x0
-#define ULP1_PAD_PTA30__JTAG_TRST_B 0x0078 0x0000 0xa 0x0
-#define ULP1_PAD_PTA30__FXIO0_D14 0x0078 0x0000 0x2 0x0
-#define ULP1_PAD_PTA30__LPSPI1_SCK 0x0078 0xd12c 0x3 0x1
-#define ULP1_PAD_PTA30__LPUART3_TX 0x0078 0xd224 0x4 0x1
-#define ULP1_PAD_PTA30__LPI2C3_HREQ 0x0078 0xd19c 0x5 0x1
-#define ULP1_PAD_PTA30__TPM2_CLKIN 0x0078 0xd1f4 0x6 0x2
-#define ULP1_PAD_PTA30__I2S1_TXD0 0x0078 0x0000 0x7 0x0
-#define ULP1_PAD_PTA31_LLWU0_P7__ADC0_CH4B 0x007c 0x0000 0x0 0x0
-#define ULP1_PAD_PTA31_LLWU0_P7__PTA31 0x007c 0x0000 0x1 0x0
-#define ULP1_PAD_PTA31_LLWU0_P7__LPTMR0_ALT1 0x007c 0x0000 0xb 0x0
-#define ULP1_PAD_PTA31_LLWU0_P7__EWM_IN 0x007c 0xd228 0xc 0x1
-#define ULP1_PAD_PTA31_LLWU0_P7__LLWU0_P7 0x007c 0x0000 0xd 0x0
-#define ULP1_PAD_PTA31_LLWU0_P7__FXIO0_D15 0x007c 0x0000 0x2 0x0
-#define ULP1_PAD_PTA31_LLWU0_P7__LPSPI1_PCS0 0x007c 0xd11c 0x3 0x2
-#define ULP1_PAD_PTA31_LLWU0_P7__LPUART3_RX 0x007c 0xd220 0x4 0x2
-#define ULP1_PAD_PTA31_LLWU0_P7__TPM2_CH0 0x007c 0xd158 0x6 0x2
-#define ULP1_PAD_PTA31_LLWU0_P7__I2S1_TXD1 0x007c 0x0000 0x7 0x0
-#define ULP1_PAD_PTB0__ADC0_CH0A 0x0080 0x0000 0x0 0x0
-#define ULP1_PAD_PTB0__PTB0 0x0080 0x0000 0x1 0x0
-#define ULP1_PAD_PTB0__CMP1_OUT 0x0080 0x0000 0xb 0x0
-#define ULP1_PAD_PTB0__EWM_OUT_B 0x0080 0x0000 0xc 0x0
-#define ULP1_PAD_PTB0__FXIO0_D16 0x0080 0x0000 0x2 0x0
-#define ULP1_PAD_PTB0__LPSPI0_SIN 0x0080 0xd114 0x3 0x3
-#define ULP1_PAD_PTB0__LPUART0_TX 0x0080 0xd200 0x4 0x3
-#define ULP1_PAD_PTB0__TPM2_CH1 0x0080 0xd15c 0x6 0x2
-#define ULP1_PAD_PTB0__CLKOUT 0x0080 0x0000 0x9 0x0
-#define ULP1_PAD_PTB1_LLWU0_P8__ADC0_CH0B 0x0084 0x0000 0x0 0x0
-#define ULP1_PAD_PTB1_LLWU0_P8__PTB1 0x0084 0x0000 0x1 0x0
-#define ULP1_PAD_PTB1_LLWU0_P8__RTC_CLKOUT 0x0084 0x0000 0xb 0x0
-#define ULP1_PAD_PTB1_LLWU0_P8__EWM_IN 0x0084 0xd228 0xc 0x2
-#define ULP1_PAD_PTB1_LLWU0_P8__LLWU0_P8 0x0084 0x0000 0xd 0x0
-#define ULP1_PAD_PTB1_LLWU0_P8__FXIO0_D17 0x0084 0x0000 0x2 0x0
-#define ULP1_PAD_PTB1_LLWU0_P8__LPSPI0_SOUT 0x0084 0xd118 0x3 0x3
-#define ULP1_PAD_PTB1_LLWU0_P8__LPUART0_RX 0x0084 0xd1fc 0x4 0x3
-#define ULP1_PAD_PTB1_LLWU0_P8__TPM3_CLKIN 0x0084 0xd1b0 0x6 0x3
-#define ULP1_PAD_PTB1_LLWU0_P8__I2S1_TX_BCLK 0x0084 0xd1d4 0x7 0x2
-#define ULP1_PAD_PTB2__ADC0_CH1A 0x0088 0x0000 0x0 0x0
-#define ULP1_PAD_PTB2__PTB2 0x0088 0x0000 0x1 0x0
-#define ULP1_PAD_PTB2__TRACE_CLKOUT 0x0088 0x0000 0xa 0x0
-#define ULP1_PAD_PTB2__FXIO0_D18 0x0088 0x0000 0x2 0x0
-#define ULP1_PAD_PTB2__LPSPI0_SCK 0x0088 0xd110 0x3 0x3
-#define ULP1_PAD_PTB2__LPUART1_TX 0x0088 0xd20c 0x4 0x3
-#define ULP1_PAD_PTB2__TPM3_CH0 0x0088 0xd160 0x6 0x2
-#define ULP1_PAD_PTB2__I2S1_TX_FS 0x0088 0xd1d8 0x7 0x2
-#define ULP1_PAD_PTB3_LLWU0_P9__ADC0_CH1B 0x008c 0x0000 0x0 0x0
-#define ULP1_PAD_PTB3_LLWU0_P9__PTB3 0x008c 0x0000 0x1 0x0
-#define ULP1_PAD_PTB3_LLWU0_P9__TRACE_D0 0x008c 0x0000 0xa 0x0
-#define ULP1_PAD_PTB3_LLWU0_P9__LPTMR1_ALT2 0x008c 0x0000 0xb 0x0
-#define ULP1_PAD_PTB3_LLWU0_P9__LLWU0_P9 0x008c 0x0000 0xd 0x0
-#define ULP1_PAD_PTB3_LLWU0_P9__FXIO0_D19 0x008c 0x0000 0x2 0x0
-#define ULP1_PAD_PTB3_LLWU0_P9__LPSPI0_PCS0 0x008c 0xd100 0x3 0x3
-#define ULP1_PAD_PTB3_LLWU0_P9__LPUART1_RX 0x008c 0xd208 0x4 0x3
-#define ULP1_PAD_PTB3_LLWU0_P9__TPM3_CH1 0x008c 0xd164 0x6 0x2
-#define ULP1_PAD_PTB3_LLWU0_P9__I2S1_TXD0 0x008c 0x0000 0x7 0x0
-#define ULP1_PAD_PTB4__PTB4 0x0090 0x0000 0x1 0x0
-#define ULP1_PAD_PTB4__TRACE_D1 0x0090 0x0000 0xa 0x0
-#define ULP1_PAD_PTB4__BOOTCFG0 0x0090 0x0000 0xd 0x0
-#define ULP1_PAD_PTB4__FXIO0_D20 0x0090 0x0000 0x2 0x0
-#define ULP1_PAD_PTB4__LPSPI0_PCS1 0x0090 0xd104 0x3 0x3
-#define ULP1_PAD_PTB4__LPUART2_TX 0x0090 0xd218 0x4 0x3
-#define ULP1_PAD_PTB4__LPI2C0_HREQ 0x0090 0xd178 0x5 0x3
-#define ULP1_PAD_PTB4__TPM3_CH2 0x0090 0xd168 0x6 0x2
-#define ULP1_PAD_PTB4__I2S1_TXD1 0x0090 0x0000 0x7 0x0
-#define ULP1_PAD_PTB5__PTB5 0x0094 0x0000 0x1 0x0
-#define ULP1_PAD_PTB5__TRACE_D2 0x0094 0x0000 0xa 0x0
-#define ULP1_PAD_PTB5__BOOTCFG1 0x0094 0x0000 0xd 0x0
-#define ULP1_PAD_PTB5__FXIO0_D21 0x0094 0x0000 0x2 0x0
-#define ULP1_PAD_PTB5__LPSPI0_PCS2 0x0094 0xd108 0x3 0x3
-#define ULP1_PAD_PTB5__LPUART2_RX 0x0094 0xd214 0x4 0x3
-#define ULP1_PAD_PTB5__LPI2C1_HREQ 0x0094 0xd184 0x5 0x3
-#define ULP1_PAD_PTB5__TPM3_CH3 0x0094 0xd16c 0x6 0x2
-#define ULP1_PAD_PTB5__I2S1_TXD2 0x0094 0x0000 0x7 0x0
-#define ULP1_PAD_PTB6_LLWU0_P10__PTB6 0x0098 0x0000 0x1 0x0
-#define ULP1_PAD_PTB6_LLWU0_P10__TRACE_D3 0x0098 0x0000 0xa 0x0
-#define ULP1_PAD_PTB6_LLWU0_P10__LPTMR1_ALT3 0x0098 0x0000 0xb 0x0
-#define ULP1_PAD_PTB6_LLWU0_P10__LLWU0_P10 0x0098 0x0000 0xd 0x0
-#define ULP1_PAD_PTB6_LLWU0_P10__FXIO0_D22 0x0098 0x0000 0x2 0x0
-#define ULP1_PAD_PTB6_LLWU0_P10__LPSPI0_PCS3 0x0098 0xd10c 0x3 0x3
-#define ULP1_PAD_PTB6_LLWU0_P10__LPUART3_TX 0x0098 0xd224 0x4 0x3
-#define ULP1_PAD_PTB6_LLWU0_P10__LPI2C0_SCL 0x0098 0xd17c 0x5 0x3
-#define ULP1_PAD_PTB6_LLWU0_P10__TPM3_CH4 0x0098 0xd170 0x6 0x2
-#define ULP1_PAD_PTB6_LLWU0_P10__I2S1_TXD3 0x0098 0x0000 0x7 0x0
-#define ULP1_PAD_PTB7_LLWU0_P11__PTB7 0x009c 0x0000 0x1 0x0
-#define ULP1_PAD_PTB7_LLWU0_P11__CMP1_OUT 0x009c 0x0000 0xb 0x0
-#define ULP1_PAD_PTB7_LLWU0_P11__LLWU0_P11 0x009c 0x0000 0xd 0x0
-#define ULP1_PAD_PTB7_LLWU0_P11__FXIO0_D23 0x009c 0x0000 0x2 0x0
-#define ULP1_PAD_PTB7_LLWU0_P11__LPSPI1_SIN 0x009c 0xd130 0x3 0x3
-#define ULP1_PAD_PTB7_LLWU0_P11__LPUART3_RX 0x009c 0xd220 0x4 0x3
-#define ULP1_PAD_PTB7_LLWU0_P11__LPI2C0_SDA 0x009c 0xd180 0x5 0x3
-#define ULP1_PAD_PTB7_LLWU0_P11__TPM3_CH5 0x009c 0xd174 0x6 0x2
-#define ULP1_PAD_PTB7_LLWU0_P11__I2S1_MCLK 0x009c 0xd1c8 0x7 0x2
-#define ULP1_PAD_PTB7_LLWU0_P11__QSPIA_SS1_B 0x009c 0x0000 0x8 0x0
-#define ULP1_PAD_PTB8__CMP0_IN0A 0x00a0 0x0000 0x0 0x0
-#define ULP1_PAD_PTB8__PTB8 0x00a0 0x0000 0x1 0x0
-#define ULP1_PAD_PTB8__RTC_CLKOUT 0x00a0 0x0000 0xb 0x0
-#define ULP1_PAD_PTB8__FXIO0_D24 0x00a0 0x0000 0x2 0x0
-#define ULP1_PAD_PTB8__LPSPI1_SOUT 0x00a0 0xd134 0x3 0x3
-#define ULP1_PAD_PTB8__LPI2C1_SCL 0x00a0 0xd188 0x5 0x3
-#define ULP1_PAD_PTB8__TPM0_CLKIN 0x00a0 0xd1a8 0x6 0x3
-#define ULP1_PAD_PTB8__I2S1_RX_BCLK 0x00a0 0xd1cc 0x7 0x2
-#define ULP1_PAD_PTB8__QSPIA_SS0_B 0x00a0 0x0000 0x8 0x0
-#define ULP1_PAD_PTB9_LLWU0_P12__CMP0_IN0B 0x00a4 0x0000 0x0 0x0
-#define ULP1_PAD_PTB9_LLWU0_P12__PTB9 0x00a4 0x0000 0x1 0x0
-#define ULP1_PAD_PTB9_LLWU0_P12__LLWU0_P12 0x00a4 0x0000 0xd 0x0
-#define ULP1_PAD_PTB9_LLWU0_P12__FXIO0_D25 0x00a4 0x0000 0x2 0x0
-#define ULP1_PAD_PTB9_LLWU0_P12__LPSPI1_SCK 0x00a4 0xd12c 0x3 0x3
-#define ULP1_PAD_PTB9_LLWU0_P12__LPI2C1_SDA 0x00a4 0xd18c 0x5 0x3
-#define ULP1_PAD_PTB9_LLWU0_P12__TPM0_CH0 0x00a4 0xd138 0x6 0x3
-#define ULP1_PAD_PTB9_LLWU0_P12__I2S1_RX_FS 0x00a4 0xd1d0 0x7 0x2
-#define ULP1_PAD_PTB9_LLWU0_P12__QSPIA_DQS 0x00a4 0x0000 0x8 0x0
-#define ULP1_PAD_PTB10__CMP0_IN1A 0x00a8 0x0000 0x0 0x0
-#define ULP1_PAD_PTB10__PTB10 0x00a8 0x0000 0x1 0x0
-#define ULP1_PAD_PTB10__TRACE_D4 0x00a8 0x0000 0xa 0x0
-#define ULP1_PAD_PTB10__FXIO0_D26 0x00a8 0x0000 0x2 0x0
-#define ULP1_PAD_PTB10__LPSPI1_PCS0 0x00a8 0xd11c 0x3 0x3
-#define ULP1_PAD_PTB10__LPI2C2_SCL 0x00a8 0xd194 0x5 0x3
-#define ULP1_PAD_PTB10__TPM0_CH1 0x00a8 0xd13c 0x6 0x3
-#define ULP1_PAD_PTB10__I2S1_RXD0 0x00a8 0xd1e4 0x7 0x2
-#define ULP1_PAD_PTB10__QSPIA_DATA7 0x00a8 0x0000 0x8 0x0
-#define ULP1_PAD_PTB11__CMP0_IN1B 0x00ac 0x0000 0x0 0x0
-#define ULP1_PAD_PTB11__PTB11 0x00ac 0x0000 0x1 0x0
-#define ULP1_PAD_PTB11__TRACE_D5 0x00ac 0x0000 0xa 0x0
-#define ULP1_PAD_PTB11__FXIO0_D27 0x00ac 0x0000 0x2 0x0
-#define ULP1_PAD_PTB11__LPSPI1_PCS1 0x00ac 0xd120 0x3 0x3
-#define ULP1_PAD_PTB11__LPI2C2_SDA 0x00ac 0xd198 0x5 0x3
-#define ULP1_PAD_PTB11__TPM1_CLKIN 0x00ac 0xd1ac 0x6 0x3
-#define ULP1_PAD_PTB11__I2S1_RXD1 0x00ac 0xd1e8 0x7 0x2
-#define ULP1_PAD_PTB11__QSPIA_DATA6 0x00ac 0x0000 0x8 0x0
-#define ULP1_PAD_PTB12__ADC1_CH0A 0x00b0 0x0000 0x0 0x0
-#define ULP1_PAD_PTB12__PTB12 0x00b0 0x0000 0x1 0x0
-#define ULP1_PAD_PTB12__TRACE_D6 0x00b0 0x0000 0xa 0x0
-#define ULP1_PAD_PTB12__FXIO0_D28 0x00b0 0x0000 0x2 0x0
-#define ULP1_PAD_PTB12__LPSPI1_PCS2 0x00b0 0xd124 0x3 0x3
-#define ULP1_PAD_PTB12__LPI2C3_SCL 0x00b0 0xd1a0 0x5 0x3
-#define ULP1_PAD_PTB12__TPM1_CH0 0x00b0 0xd150 0x6 0x3
-#define ULP1_PAD_PTB12__I2S1_RXD2 0x00b0 0xd1ec 0x7 0x2
-#define ULP1_PAD_PTB12__QSPIA_DATA5 0x00b0 0x0000 0x8 0x0
-#define ULP1_PAD_PTB13__ADC1_CH0B 0x00b4 0x0000 0x0 0x0
-#define ULP1_PAD_PTB13__PTB13 0x00b4 0x0000 0x1 0x0
-#define ULP1_PAD_PTB13__TRACE_D7 0x00b4 0x0000 0xa 0x0
-#define ULP1_PAD_PTB13__FXIO0_D29 0x00b4 0x0000 0x2 0x0
-#define ULP1_PAD_PTB13__LPSPI1_PCS3 0x00b4 0xd128 0x3 0x3
-#define ULP1_PAD_PTB13__LPI2C3_SDA 0x00b4 0xd1a4 0x5 0x3
-#define ULP1_PAD_PTB13__TPM1_CH1 0x00b4 0xd154 0x6 0x3
-#define ULP1_PAD_PTB13__I2S1_RXD3 0x00b4 0xd1f0 0x7 0x2
-#define ULP1_PAD_PTB13__QSPIA_DATA4 0x00b4 0x0000 0x8 0x0
-#define ULP1_PAD_PTB14_LLWU0_P13__ADC1_CH1A 0x00b8 0x0000 0x0 0x0
-#define ULP1_PAD_PTB14_LLWU0_P13__PTB14 0x00b8 0x0000 0x1 0x0
-#define ULP1_PAD_PTB14_LLWU0_P13__LLWU0_P13 0x00b8 0x0000 0xd 0x0
-#define ULP1_PAD_PTB14_LLWU0_P13__FXIO0_D30 0x00b8 0x0000 0x2 0x0
-#define ULP1_PAD_PTB14_LLWU0_P13__LPI2C2_HREQ 0x00b8 0xd190 0x5 0x3
-#define ULP1_PAD_PTB14_LLWU0_P13__TPM2_CLKIN 0x00b8 0xd1f4 0x6 0x3
-#define ULP1_PAD_PTB14_LLWU0_P13__QSPIA_SS0_B 0x00b8 0x0000 0x8 0x0
-#define ULP1_PAD_PTB14_LLWU0_P13__QSPIA_SCLK_B 0x00b8 0x0000 0x9 0x0
-#define ULP1_PAD_PTB15__ADC1_CH1B 0x00bc 0x0000 0x0 0x0
-#define ULP1_PAD_PTB15__PTB15 0x00bc 0x0000 0x1 0x0
-#define ULP1_PAD_PTB15__FXIO0_D31 0x00bc 0x0000 0x2 0x0
-#define ULP1_PAD_PTB15__LPI2C3_HREQ 0x00bc 0xd19c 0x5 0x3
-#define ULP1_PAD_PTB15__TPM2_CH0 0x00bc 0xd158 0x6 0x3
-#define ULP1_PAD_PTB15__QSPIA_SCLK 0x00bc 0x0000 0x8 0x0
-#define ULP1_PAD_PTB16_LLWU0_P14__ADC0_CH2A 0x00c0 0x0000 0x0 0x0
-#define ULP1_PAD_PTB16_LLWU0_P14__PTB16 0x00c0 0x0000 0x1 0x0
-#define ULP1_PAD_PTB16_LLWU0_P14__LLWU0_P14 0x00c0 0x0000 0xd 0x0
-#define ULP1_PAD_PTB16_LLWU0_P14__TPM2_CH1 0x00c0 0xd15c 0x6 0x3
-#define ULP1_PAD_PTB16_LLWU0_P14__QSPIA_DATA3 0x00c0 0x0000 0x8 0x0
-#define ULP1_PAD_PTB17__ADC0_CH2B 0x00c4 0x0000 0x0 0x0
-#define ULP1_PAD_PTB17__PTB17 0x00c4 0x0000 0x1 0x0
-#define ULP1_PAD_PTB17__TPM3_CLKIN 0x00c4 0xd1b0 0x6 0x2
-#define ULP1_PAD_PTB17__QSPIA_DATA2 0x00c4 0x0000 0x8 0x0
-#define ULP1_PAD_PTB18__ADC0_CH3A 0x00c8 0x0000 0x0 0x0
-#define ULP1_PAD_PTB18__PTB18 0x00c8 0x0000 0x1 0x0
-#define ULP1_PAD_PTB18__TPM3_CH0 0x00c8 0xd160 0x6 0x3
-#define ULP1_PAD_PTB18__QSPIA_DATA1 0x00c8 0x0000 0x8 0x0
-#define ULP1_PAD_PTB19_LLWU0_P15__ADC0_CH3B 0x00cc 0x0000 0x0 0x0
-#define ULP1_PAD_PTB19_LLWU0_P15__PTB19 0x00cc 0x0000 0x1 0x0
-#define ULP1_PAD_PTB19_LLWU0_P15__USB0_ID 0x00cc 0x0000 0xa 0x0
-#define ULP1_PAD_PTB19_LLWU0_P15__LLWU0_P15 0x00cc 0x0000 0xd 0x0
-#define ULP1_PAD_PTB19_LLWU0_P15__TPM3_CH1 0x00cc 0xd164 0x6 0x3
-#define ULP1_PAD_PTB19_LLWU0_P15__QSPIA_DATA0 0x00cc 0x0000 0x8 0x0
-#define ULP1_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
-#define ULP1_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
-#define ULP1_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
-#define ULP1_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
-#define ULP1_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
-#define ULP1_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
-#define ULP1_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
-#define ULP1_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
-#define ULP1_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
-#define ULP1_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
-#define ULP1_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1
-#define ULP1_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0
-#define ULP1_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0
-#define ULP1_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0
-#define ULP1_PAD_PTC2__LPUART4_TX 0x0008 0x024c 0x4 0x1
-#define ULP1_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1
-#define ULP1_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1
-#define ULP1_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0
-#define ULP1_PAD_PTC3__PTC3 0x000c 0x0000 0x1 0x0
-#define ULP1_PAD_PTC3__TRACE_D12 0x000c 0x0000 0xa 0x0
-#define ULP1_PAD_PTC3__LPUART4_RX 0x000c 0x0248 0x4 0x1
-#define ULP1_PAD_PTC3__TPM4_CH2 0x000c 0x0288 0x6 0x1
-#define ULP1_PAD_PTC3__FB_AD3 0x000c 0x0000 0x9 0x0
-#define ULP1_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0
-#define ULP1_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0
-#define ULP1_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1
-#define ULP1_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1
-#define ULP1_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1
-#define ULP1_PAD_PTC4__LPI2C5_SCL 0x0010 0x02bc 0x5 0x1
-#define ULP1_PAD_PTC4__TPM4_CH3 0x0010 0x028c 0x6 0x1
-#define ULP1_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0
-#define ULP1_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0
-#define ULP1_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0
-#define ULP1_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1
-#define ULP1_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1
-#define ULP1_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0
-#define ULP1_PAD_PTC5__LPI2C5_SDA 0x0014 0x02c0 0x5 0x1
-#define ULP1_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1
-#define ULP1_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0
-#define ULP1_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0
-#define ULP1_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0
-#define ULP1_PAD_PTC6__FXIO1_D2 0x0018 0x020c 0x2 0x1
-#define ULP1_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1
-#define ULP1_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1
-#define ULP1_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02b8 0x5 0x1
-#define ULP1_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1
-#define ULP1_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0
-#define ULP1_PAD_PTC7__PTC7 0x001c 0x0000 0x1 0x0
-#define ULP1_PAD_PTC7__TRACE_D8 0x001c 0x0000 0xa 0x0
-#define ULP1_PAD_PTC7__FXIO1_D3 0x001c 0x0210 0x2 0x1
-#define ULP1_PAD_PTC7__LPUART5_RX 0x001c 0x0254 0x4 0x1
-#define ULP1_PAD_PTC7__TPM5_CH1 0x001c 0x02c8 0x6 0x1
-#define ULP1_PAD_PTC7__FB_AD7 0x001c 0x0000 0x9 0x0
-#define ULP1_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0
-#define ULP1_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0
-#define ULP1_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1
-#define ULP1_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1
-#define ULP1_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025c 0x4 0x1
-#define ULP1_PAD_PTC8__LPI2C6_SCL 0x0020 0x02fc 0x5 0x1
-#define ULP1_PAD_PTC8__TPM5_CLKIN 0x0020 0x02cc 0x6 0x1
-#define ULP1_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0
-#define ULP1_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0
-#define ULP1_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0
-#define ULP1_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1
-#define ULP1_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1
-#define ULP1_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0
-#define ULP1_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1
-#define ULP1_PAD_PTC9__TPM5_CH0 0x0024 0x02c4 0x6 0x1
-#define ULP1_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0
-#define ULP1_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0
-#define ULP1_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0
-#define ULP1_PAD_PTC10__FXIO1_D6 0x0028 0x021c 0x2 0x1
-#define ULP1_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1
-#define ULP1_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1
-#define ULP1_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02f8 0x5 0x1
-#define ULP1_PAD_PTC10__TPM7_CH3 0x0028 0x02e8 0x6 0x1
-#define ULP1_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0
-#define ULP1_PAD_PTC11__PTC11 0x002c 0x0000 0x1 0x0
-#define ULP1_PAD_PTC11__TRACE_D4 0x002c 0x0000 0xa 0x0
-#define ULP1_PAD_PTC11__FXIO1_D7 0x002c 0x0220 0x2 0x1
-#define ULP1_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1
-#define ULP1_PAD_PTC11__LPUART6_RX 0x002c 0x0260 0x4 0x1
-#define ULP1_PAD_PTC11__TPM7_CH4 0x002c 0x02ec 0x6 0x1
-#define ULP1_PAD_PTC11__FB_AD11 0x002c 0x0000 0x9 0x0
-#define ULP1_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0
-#define ULP1_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0
-#define ULP1_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1
-#define ULP1_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1
-#define ULP1_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1
-#define ULP1_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1
-#define ULP1_PAD_PTC12__TPM7_CH5 0x0030 0x02f0 0x6 0x1
-#define ULP1_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0
-#define ULP1_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0
-#define ULP1_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0
-#define ULP1_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1
-#define ULP1_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1
-#define ULP1_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0
-#define ULP1_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1
-#define ULP1_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1
-#define ULP1_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0
-#define ULP1_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0
-#define ULP1_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0
-#define ULP1_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1
-#define ULP1_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1
-#define ULP1_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1
-#define ULP1_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1
-#define ULP1_PAD_PTC14__TPM7_CH0 0x0038 0x02dc 0x6 0x1
-#define ULP1_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0
-#define ULP1_PAD_PTC15__PTC15 0x003c 0x0000 0x1 0x0
-#define ULP1_PAD_PTC15__TRACE_D0 0x003c 0x0000 0xa 0x0
-#define ULP1_PAD_PTC15__FXIO1_D11 0x003c 0x0230 0x2 0x1
-#define ULP1_PAD_PTC15__LPUART7_RX 0x003c 0x026c 0x4 0x1
-#define ULP1_PAD_PTC15__TPM7_CH1 0x003c 0x02e0 0x6 0x1
-#define ULP1_PAD_PTC15__FB_AD15 0x003c 0x0000 0x9 0x0
-#define ULP1_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0
-#define ULP1_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0
-#define ULP1_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1
-#define ULP1_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1
-#define ULP1_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1
-#define ULP1_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0
-#define ULP1_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0
-#define ULP1_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1
-#define ULP1_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1
-#define ULP1_PAD_PTC17__TPM6_CLKIN 0x0044 0x02d8 0x6 0x1
-#define ULP1_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0
-#define ULP1_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0
-#define ULP1_PAD_PTC18__FXIO1_D14 0x0048 0x023c 0x2 0x1
-#define ULP1_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1
-#define ULP1_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1
-#define ULP1_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0
-#define ULP1_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0
-#define ULP1_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1
-#define ULP1_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1
-#define ULP1_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1
-#define ULP1_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0
-#define ULP1_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0
-#define ULP1_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0
-#define ULP1_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0
-#define ULP1_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0
-#define ULP1_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0
-#define ULP1_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0
-#define ULP1_PAD_PTD3__PTD3 0x008c 0x0000 0x1 0x0
-#define ULP1_PAD_PTD3__SDHC0_D7 0x008c 0x0000 0x8 0x0
-#define ULP1_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0
-#define ULP1_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0
-#define ULP1_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0
-#define ULP1_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0
-#define ULP1_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0
-#define ULP1_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0
-#define ULP1_PAD_PTD7__PTD7 0x009c 0x0000 0x1 0x0
-#define ULP1_PAD_PTD7__SDHC0_D3 0x009c 0x0000 0x8 0x0
-#define ULP1_PAD_PTD8__PTD8 0x00a0 0x0000 0x1 0x0
-#define ULP1_PAD_PTD8__TPM4_CLKIN 0x00a0 0x0298 0x6 0x2
-#define ULP1_PAD_PTD8__SDHC0_D2 0x00a0 0x0000 0x8 0x0
-#define ULP1_PAD_PTD9__PTD9 0x00a4 0x0000 0x1 0x0
-#define ULP1_PAD_PTD9__TPM4_CH0 0x00a4 0x0280 0x6 0x2
-#define ULP1_PAD_PTD9__SDHC0_D1 0x00a4 0x0000 0x8 0x0
-#define ULP1_PAD_PTD10__PTD10 0x00a8 0x0000 0x1 0x0
-#define ULP1_PAD_PTD10__TPM4_CH1 0x00a8 0x0284 0x6 0x2
-#define ULP1_PAD_PTD10__SDHC0_D0 0x00a8 0x0000 0x8 0x0
-#define ULP1_PAD_PTD11__PTD11 0x00ac 0x0000 0x1 0x0
-#define ULP1_PAD_PTD11__TPM4_CH2 0x00ac 0x0288 0x6 0x2
-#define ULP1_PAD_PTD11__SDHC0_DQS 0x00ac 0x0000 0x8 0x0
-#define ULP1_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0
-#define ULP1_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0
-#define ULP1_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02a0 0x3 0x2
-#define ULP1_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2
-#define ULP1_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2
-#define ULP1_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0
-#define ULP1_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0
-#define ULP1_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0
-#define ULP1_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0
-#define ULP1_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02a4 0x3 0x2
-#define ULP1_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0
-#define ULP1_PAD_PTE1__LPI2C4_SDA 0x0104 0x027c 0x5 0x2
-#define ULP1_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0
-#define ULP1_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0
-#define ULP1_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0
-#define ULP1_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0
-#define ULP1_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02a8 0x3 0x2
-#define ULP1_PAD_PTE2__LPUART4_TX 0x0108 0x024c 0x4 0x2
-#define ULP1_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2
-#define ULP1_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0
-#define ULP1_PAD_PTE3__PTE3 0x010c 0x0000 0x1 0x0
-#define ULP1_PAD_PTE3__FXIO1_D28 0x010c 0x0000 0x2 0x0
-#define ULP1_PAD_PTE3__LPUART4_RX 0x010c 0x0248 0x4 0x2
-#define ULP1_PAD_PTE3__TPM5_CH1 0x010c 0x02c8 0x6 0x2
-#define ULP1_PAD_PTE3__SDHC1_CMD 0x010c 0x0000 0x8 0x0
-#define ULP1_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0
-#define ULP1_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0
-#define ULP1_PAD_PTE4__LPSPI2_SIN 0x0110 0x02b0 0x3 0x2
-#define ULP1_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2
-#define ULP1_PAD_PTE4__LPI2C5_SCL 0x0110 0x02bc 0x5 0x2
-#define ULP1_PAD_PTE4__TPM5_CLKIN 0x0110 0x02cc 0x6 0x2
-#define ULP1_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0
-#define ULP1_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0
-#define ULP1_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0
-#define ULP1_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02b4 0x3 0x2
-#define ULP1_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0
-#define ULP1_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2
-#define ULP1_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2
-#define ULP1_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0
-#define ULP1_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0
-#define ULP1_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0
-#define ULP1_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2
-#define ULP1_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2
-#define ULP1_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02b8 0x5 0x2
-#define ULP1_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2
-#define ULP1_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0
-#define ULP1_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0
-#define ULP1_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0
-#define ULP1_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0
-#define ULP1_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0
-#define ULP1_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0
-#define ULP1_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2
-#define ULP1_PAD_PTE7__LPUART5_RX 0x011c 0x0254 0x4 0x2
-#define ULP1_PAD_PTE7__TPM7_CH4 0x011c 0x02ec 0x6 0x2
-#define ULP1_PAD_PTE7__SDHC1_D5 0x011c 0x0000 0x8 0x0
-#define ULP1_PAD_PTE7__FB_A18 0x011c 0x0000 0x9 0x0
-#define ULP1_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0
-#define ULP1_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0
-#define ULP1_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0
-#define ULP1_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0
-#define ULP1_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2
-#define ULP1_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025c 0x4 0x2
-#define ULP1_PAD_PTE8__LPI2C6_SCL 0x0120 0x02fc 0x5 0x2
-#define ULP1_PAD_PTE8__TPM7_CH5 0x0120 0x02f0 0x6 0x2
-#define ULP1_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1
-#define ULP1_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0
-#define ULP1_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0
-#define ULP1_PAD_PTE9__PTE9 0x0124 0x0000 0x1 0x0
-#define ULP1_PAD_PTE9__TRACE_D5 0x0124 0x0000 0xa 0x0
-#define ULP1_PAD_PTE9__VIU_D17 0x0124 0x0000 0xc 0x0
-#define ULP1_PAD_PTE9__FXIO1_D22 0x0124 0x0000 0x2 0x0
-#define ULP1_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2
-#define ULP1_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0
-#define ULP1_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2
-#define ULP1_PAD_PTE9__TPM7_CLKIN 0x0124 0x02f4 0x6 0x2
-#define ULP1_PAD_PTE9__SDHC1_CD 0x0124 0x032c 0x7 0x1
-#define ULP1_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0
-#define ULP1_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0
-#define ULP1_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0
-#define ULP1_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0
-#define ULP1_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0
-#define ULP1_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0
-#define ULP1_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031c 0x3 0x2
-#define ULP1_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2
-#define ULP1_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02f8 0x5 0x2
-#define ULP1_PAD_PTE10__TPM7_CH0 0x0128 0x02dc 0x6 0x2
-#define ULP1_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0
-#define ULP1_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0
-#define ULP1_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0
-#define ULP1_PAD_PTE11__PTE11 0x012c 0x0000 0x1 0x0
-#define ULP1_PAD_PTE11__TRACE_D3 0x012c 0x0000 0xa 0x0
-#define ULP1_PAD_PTE11__VIU_D19 0x012c 0x0000 0xc 0x0
-#define ULP1_PAD_PTE11__FXIO1_D20 0x012c 0x0000 0x2 0x0
-#define ULP1_PAD_PTE11__LPUART6_RX 0x012c 0x0260 0x4 0x2
-#define ULP1_PAD_PTE11__TPM7_CH1 0x012c 0x02e0 0x6 0x2
-#define ULP1_PAD_PTE11__SDHC1_RESET_B 0x012c 0x0000 0x8 0x0
-#define ULP1_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0
-#define ULP1_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0
-#define ULP1_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0
-#define ULP1_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0
-#define ULP1_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0
-#define ULP1_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2
-#define ULP1_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2
-#define ULP1_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2
-#define ULP1_PAD_PTE12__TPM7_CH2 0x0130 0x02e4 0x6 0x2
-#define ULP1_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2
-#define ULP1_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0
-#define ULP1_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0
-#define ULP1_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0
-#define ULP1_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0
-#define ULP1_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0
-#define ULP1_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2
-#define ULP1_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0
-#define ULP1_PAD_PTE13__LPI2C7_SDA 0x0134 0x030c 0x5 0x2
-#define ULP1_PAD_PTE13__TPM6_CLKIN 0x0134 0x02d8 0x6 0x2
-#define ULP1_PAD_PTE13__SDHC1_CD 0x0134 0x032c 0x8 0x2
-#define ULP1_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0
-#define ULP1_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0
-#define ULP1_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0
-#define ULP1_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0
-#define ULP1_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0
-#define ULP1_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2
-#define ULP1_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2
-#define ULP1_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2
-#define ULP1_PAD_PTE14__TPM6_CH0 0x0138 0x02d0 0x6 0x2
-#define ULP1_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0
-#define ULP1_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0
-#define ULP1_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0
-#define ULP1_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0
-#define ULP1_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0
-#define ULP1_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0
-#define ULP1_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2
-#define ULP1_PAD_PTE15__LPUART7_RX 0x013c 0x026c 0x4 0x2
-#define ULP1_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2
-#define ULP1_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0
-#define ULP1_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0
-#define ULP1_PAD_PTF0__VIU_DE 0x0180 0x0000 0xc 0x0
-#define ULP1_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3
-#define ULP1_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3
-#define ULP1_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3
-#define ULP1_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0
-#define ULP1_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0
-#define ULP1_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0
-#define ULP1_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0
-#define ULP1_PAD_PTF1__LPI2C4_SDA 0x0184 0x027c 0x5 0x3
-#define ULP1_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3
-#define ULP1_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0
-#define ULP1_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0
-#define ULP1_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0
-#define ULP1_PAD_PTF2__LPUART4_TX 0x0188 0x024c 0x4 0x3
-#define ULP1_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3
-#define ULP1_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3
-#define ULP1_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0
-#define ULP1_PAD_PTF3__PTF3 0x018c 0x0000 0x1 0x0
-#define ULP1_PAD_PTF3__VIU_PCLK 0x018c 0x0000 0xc 0x0
-#define ULP1_PAD_PTF3__LPUART4_RX 0x018c 0x0248 0x4 0x3
-#define ULP1_PAD_PTF3__TPM4_CH2 0x018c 0x0288 0x6 0x3
-#define ULP1_PAD_PTF3__FB_AD16 0x018c 0x0000 0x9 0x0
-#define ULP1_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0
-#define ULP1_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0
-#define ULP1_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2
-#define ULP1_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02a0 0x3 0x3
-#define ULP1_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3
-#define ULP1_PAD_PTF4__LPI2C5_SCL 0x0190 0x02bc 0x5 0x3
-#define ULP1_PAD_PTF4__TPM4_CH3 0x0190 0x028c 0x6 0x2
-#define ULP1_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0
-#define ULP1_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0
-#define ULP1_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0
-#define ULP1_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2
-#define ULP1_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02a4 0x3 0x3
-#define ULP1_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0
-#define ULP1_PAD_PTF5__LPI2C5_SDA 0x0194 0x02c0 0x5 0x3
-#define ULP1_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2
-#define ULP1_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0
-#define ULP1_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0
-#define ULP1_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0
-#define ULP1_PAD_PTF6__FXIO1_D2 0x0198 0x020c 0x2 0x2
-#define ULP1_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02a8 0x3 0x3
-#define ULP1_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3
-#define ULP1_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02b8 0x5 0x3
-#define ULP1_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2
-#define ULP1_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0
-#define ULP1_PAD_PTF7__PTF7 0x019c 0x0000 0x1 0x0
-#define ULP1_PAD_PTF7__VIU_D3 0x019c 0x0000 0xc 0x0
-#define ULP1_PAD_PTF7__FXIO1_D3 0x019c 0x0210 0x2 0x2
-#define ULP1_PAD_PTF7__LPUART5_RX 0x019c 0x0254 0x4 0x3
-#define ULP1_PAD_PTF7__TPM5_CH1 0x019c 0x02c8 0x6 0x3
-#define ULP1_PAD_PTF7__FB_AD20 0x019c 0x0000 0x9 0x0
-#define ULP1_PAD_PTF8__PTF8 0x01a0 0x0000 0x1 0x0
-#define ULP1_PAD_PTF8__USB1_ULPI_CLK 0x01a0 0x0000 0xb 0x0
-#define ULP1_PAD_PTF8__VIU_D4 0x01a0 0x0000 0xc 0x0
-#define ULP1_PAD_PTF8__FXIO1_D4 0x01a0 0x0214 0x2 0x2
-#define ULP1_PAD_PTF8__LPSPI2_SIN 0x01a0 0x02b0 0x3 0x3
-#define ULP1_PAD_PTF8__LPUART6_CTS_B 0x01a0 0x025c 0x4 0x3
-#define ULP1_PAD_PTF8__LPI2C6_SCL 0x01a0 0x02fc 0x5 0x3
-#define ULP1_PAD_PTF8__TPM5_CLKIN 0x01a0 0x02cc 0x6 0x3
-#define ULP1_PAD_PTF8__FB_AD21 0x01a0 0x0000 0x9 0x0
-#define ULP1_PAD_PTF9__PTF9 0x01a4 0x0000 0x1 0x0
-#define ULP1_PAD_PTF9__USB1_ULPI_NXT 0x01a4 0x0000 0xb 0x0
-#define ULP1_PAD_PTF9__VIU_D5 0x01a4 0x0000 0xc 0x0
-#define ULP1_PAD_PTF9__FXIO1_D5 0x01a4 0x0218 0x2 0x2
-#define ULP1_PAD_PTF9__LPSPI2_SOUT 0x01a4 0x02b4 0x3 0x3
-#define ULP1_PAD_PTF9__LPUART6_RTS_B 0x01a4 0x0000 0x4 0x0
-#define ULP1_PAD_PTF9__LPI2C6_SDA 0x01a4 0x0300 0x5 0x3
-#define ULP1_PAD_PTF9__TPM5_CH0 0x01a4 0x02c4 0x6 0x3
-#define ULP1_PAD_PTF9__FB_AD22 0x01a4 0x0000 0x9 0x0
-#define ULP1_PAD_PTF10__PTF10 0x01a8 0x0000 0x1 0x0
-#define ULP1_PAD_PTF10__USB1_ULPI_STP 0x01a8 0x0000 0xb 0x0
-#define ULP1_PAD_PTF10__VIU_D6 0x01a8 0x0000 0xc 0x0
-#define ULP1_PAD_PTF10__FXIO1_D6 0x01a8 0x021c 0x2 0x2
-#define ULP1_PAD_PTF10__LPSPI2_SCK 0x01a8 0x02ac 0x3 0x3
-#define ULP1_PAD_PTF10__LPUART6_TX 0x01a8 0x0264 0x4 0x3
-#define ULP1_PAD_PTF10__LPI2C6_HREQ 0x01a8 0x02f8 0x5 0x3
-#define ULP1_PAD_PTF10__TPM7_CH3 0x01a8 0x02e8 0x6 0x3
-#define ULP1_PAD_PTF10__FB_AD23 0x01a8 0x0000 0x9 0x0
-#define ULP1_PAD_PTF11__PTF11 0x01ac 0x0000 0x1 0x0
-#define ULP1_PAD_PTF11__USB1_ULPI_DIR 0x01ac 0x0000 0xb 0x0
-#define ULP1_PAD_PTF11__VIU_D7 0x01ac 0x0000 0xc 0x0
-#define ULP1_PAD_PTF11__FXIO1_D7 0x01ac 0x0220 0x2 0x2
-#define ULP1_PAD_PTF11__LPSPI2_PCS0 0x01ac 0x029c 0x3 0x3
-#define ULP1_PAD_PTF11__LPUART6_RX 0x01ac 0x0260 0x4 0x3
-#define ULP1_PAD_PTF11__TPM7_CH4 0x01ac 0x02ec 0x6 0x3
-#define ULP1_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01ac 0x0000 0x9 0x0
-#define ULP1_PAD_PTF12__PTF12 0x01b0 0x0000 0x1 0x0
-#define ULP1_PAD_PTF12__USB1_ULPI_DATA0 0x01b0 0x0000 0xb 0x0
-#define ULP1_PAD_PTF12__VIU_D8 0x01b0 0x0000 0xc 0x0
-#define ULP1_PAD_PTF12__FXIO1_D8 0x01b0 0x0224 0x2 0x2
-#define ULP1_PAD_PTF12__LPSPI3_PCS1 0x01b0 0x0314 0x3 0x3
-#define ULP1_PAD_PTF12__LPUART7_CTS_B 0x01b0 0x0268 0x4 0x3
-#define ULP1_PAD_PTF12__LPI2C7_SCL 0x01b0 0x0308 0x5 0x3
-#define ULP1_PAD_PTF12__TPM7_CH5 0x01b0 0x02f0 0x6 0x3
-#define ULP1_PAD_PTF12__FB_AD24 0x01b0 0x0000 0x9 0x0
-#define ULP1_PAD_PTF13__PTF13 0x01b4 0x0000 0x1 0x0
-#define ULP1_PAD_PTF13__USB1_ULPI_DATA1 0x01b4 0x0000 0xb 0x0
-#define ULP1_PAD_PTF13__VIU_D9 0x01b4 0x0000 0xc 0x0
-#define ULP1_PAD_PTF13__FXIO1_D9 0x01b4 0x0228 0x2 0x2
-#define ULP1_PAD_PTF13__LPSPI3_PCS2 0x01b4 0x0318 0x3 0x3
-#define ULP1_PAD_PTF13__LPUART7_RTS_B 0x01b4 0x0000 0x4 0x0
-#define ULP1_PAD_PTF13__LPI2C7_SDA 0x01b4 0x030c 0x5 0x3
-#define ULP1_PAD_PTF13__TPM7_CLKIN 0x01b4 0x02f4 0x6 0x3
-#define ULP1_PAD_PTF13__FB_AD25 0x01b4 0x0000 0x9 0x0
-#define ULP1_PAD_PTF14__PTF14 0x01b8 0x0000 0x1 0x0
-#define ULP1_PAD_PTF14__USB1_ULPI_DATA2 0x01b8 0x0000 0xb 0x0
-#define ULP1_PAD_PTF14__VIU_D10 0x01b8 0x0000 0xc 0x0
-#define ULP1_PAD_PTF14__FXIO1_D10 0x01b8 0x022c 0x2 0x2
-#define ULP1_PAD_PTF14__LPSPI3_PCS3 0x01b8 0x031c 0x3 0x3
-#define ULP1_PAD_PTF14__LPUART7_TX 0x01b8 0x0270 0x4 0x3
-#define ULP1_PAD_PTF14__LPI2C7_HREQ 0x01b8 0x0304 0x5 0x3
-#define ULP1_PAD_PTF14__TPM7_CH0 0x01b8 0x02dc 0x6 0x3
-#define ULP1_PAD_PTF14__FB_AD26 0x01b8 0x0000 0x9 0x0
-#define ULP1_PAD_PTF15__PTF15 0x01bc 0x0000 0x1 0x0
-#define ULP1_PAD_PTF15__USB1_ULPI_DATA3 0x01bc 0x0000 0xb 0x0
-#define ULP1_PAD_PTF15__VIU_D11 0x01bc 0x0000 0xc 0x0
-#define ULP1_PAD_PTF15__FXIO1_D11 0x01bc 0x0230 0x2 0x2
-#define ULP1_PAD_PTF15__LPUART7_RX 0x01bc 0x026c 0x4 0x3
-#define ULP1_PAD_PTF15__TPM7_CH1 0x01bc 0x02e0 0x6 0x3
-#define ULP1_PAD_PTF15__FB_AD27 0x01bc 0x0000 0x9 0x0
-#define ULP1_PAD_PTF16__PTF16 0x01c0 0x0000 0x1 0x0
-#define ULP1_PAD_PTF16__USB1_ULPI_DATA4 0x01c0 0x0000 0xb 0x0
-#define ULP1_PAD_PTF16__VIU_D12 0x01c0 0x0000 0xc 0x0
-#define ULP1_PAD_PTF16__FXIO1_D12 0x01c0 0x0234 0x2 0x2
-#define ULP1_PAD_PTF16__LPSPI3_SIN 0x01c0 0x0324 0x3 0x3
-#define ULP1_PAD_PTF16__TPM7_CH2 0x01c0 0x02e4 0x6 0x3
-#define ULP1_PAD_PTF16__FB_AD28 0x01c0 0x0000 0x9 0x0
-#define ULP1_PAD_PTF17__PTF17 0x01c4 0x0000 0x1 0x0
-#define ULP1_PAD_PTF17__USB1_ULPI_DATA5 0x01c4 0x0000 0xb 0x0
-#define ULP1_PAD_PTF17__VIU_D13 0x01c4 0x0000 0xc 0x0
-#define ULP1_PAD_PTF17__FXIO1_D13 0x01c4 0x0238 0x2 0x2
-#define ULP1_PAD_PTF17__LPSPI3_SOUT 0x01c4 0x0328 0x3 0x3
-#define ULP1_PAD_PTF17__TPM6_CLKIN 0x01c4 0x02d8 0x6 0x3
-#define ULP1_PAD_PTF17__FB_AD29 0x01c4 0x0000 0x9 0x0
-#define ULP1_PAD_PTF18__PTF18 0x01c8 0x0000 0x1 0x0
-#define ULP1_PAD_PTF18__USB1_ULPI_DATA6 0x01c8 0x0000 0xb 0x0
-#define ULP1_PAD_PTF18__VIU_D14 0x01c8 0x0000 0xc 0x0
-#define ULP1_PAD_PTF18__FXIO1_D14 0x01c8 0x023c 0x2 0x2
-#define ULP1_PAD_PTF18__LPSPI3_SCK 0x01c8 0x0320 0x3 0x3
-#define ULP1_PAD_PTF18__TPM6_CH0 0x01c8 0x02d0 0x6 0x3
-#define ULP1_PAD_PTF18__FB_AD30 0x01c8 0x0000 0x9 0x0
-#define ULP1_PAD_PTF19__PTF19 0x01cc 0x0000 0x1 0x0
-#define ULP1_PAD_PTF19__USB1_ULPI_DATA7 0x01cc 0x0000 0xb 0x0
-#define ULP1_PAD_PTF19__VIU_D15 0x01cc 0x0000 0xc 0x0
-#define ULP1_PAD_PTF19__FXIO1_D15 0x01cc 0x0240 0x2 0x2
-#define ULP1_PAD_PTF19__LPSPI3_PCS0 0x01cc 0x0310 0x3 0x3
-#define ULP1_PAD_PTF19__TPM6_CH1 0x01cc 0x02d4 0x6 0x3
-#define ULP1_PAD_PTF19__FB_AD31 0x01cc 0x0000 0x9 0x0
-
-#endif /* __DTS_ULP1_PINFUNC_H */
+#endif /* __DTS_IMX7ULP_PINFUNC_H */
diff --git a/arch/arm/dts/imx7ulp.dtsi b/arch/arm/dts/imx7ulp.dtsi
index a8458f89d5..7bcd2cc346 100644
--- a/arch/arm/dts/imx7ulp.dtsi
+++ b/arch/arm/dts/imx7ulp.dtsi
@@ -16,10 +16,12 @@
interrupt-parent = <&intc>;
aliases {
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- gpio2 = &gpio2;
- gpio3 = &gpio3;
+ gpio0 = &gpio4;
+ gpio1 = &gpio5;
+ gpio2 = &gpio0;
+ gpio3 = &gpio1;
+ gpio4 = &gpio2;
+ gpio5 = &gpio3;
mmc0 = &usdhc0;
mmc1 = &usdhc1;
serial0 = &lpuart4;
@@ -27,10 +29,12 @@
serial2 = &lpuart6;
serial3 = &lpuart7;
usbphy0 = &usbphy1;
+ usb0 = &usbotg1;
i2c4 = &lpi2c4;
i2c5 = &lpi2c5;
i2c6 = &lpi2c6;
i2c7 = &lpi2c7;
+ spi0 = &qspi1;
};
cpus {
@@ -503,6 +507,22 @@
fsl,mux_mask = <0xf00>;
};
+ gpio4: gpio at 4103f000 {
+ compatible = "fsl,imx7ulp-gpio";
+ reg = <0x4103f000 0x1000 0x4100F000 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&iomuxc 0 0 32>;
+ };
+
+ gpio5: gpio at 41040000 {
+ compatible = "fsl,imx7ulp-gpio";
+ reg = <0x41040000 0x1000 0x4100F040 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&iomuxc 0 32 32>;
+ };
+
gpio0: gpio at 40ae0000 {
compatible = "fsl,imx7ulp-gpio";
reg = <0x40ae0000 0x1000 0x400F0000 0x40>;
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v2 6/6] mx7ulp: Add support for Embedded Artists COM board
2019-10-30 13:41 [U-Boot] [PATCH v2 1/6] mx7ulp: Print the LDO mode status Fabio Estevam
` (3 preceding siblings ...)
2019-10-30 13:41 ` [U-Boot] [PATCH v2 5/6] mx7ulp: Sync the device tree related files Fabio Estevam
@ 2019-10-30 13:41 ` Fabio Estevam
2019-11-05 5:57 ` Peng Fan
4 siblings, 1 reply; 8+ messages in thread
From: Fabio Estevam @ 2019-10-30 13:41 UTC (permalink / raw)
To: u-boot
The Embedded Artists COM board is based on NXP i.MX7ULP.
It has a BD70528 PMIC from Rohm with discrete DCDC powering option and
improved current observability (compared to the existing NXP i.MX7ULP EVK).
Add the initial support for the board.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
Changes since v1:
- Lower the DDR frequency inside DCD as it is safer (Ye Li)
- Drop CONFIG_IMX7ULP_LOWER_DDR_FREQUENCY=y
arch/arm/dts/Makefile | 3 +-
arch/arm/mach-imx/mx7ulp/Kconfig | 6 ++
board/ea/mx7ulp_com/Kconfig | 12 +++
board/ea/mx7ulp_com/MAINTAINERS | 6 ++
board/ea/mx7ulp_com/Makefile | 6 ++
board/ea/mx7ulp_com/imximage.cfg | 137 +++++++++++++++++++++++++++++++
board/ea/mx7ulp_com/mx7ulp_com.c | 48 +++++++++++
configs/mx7ulp_com_defconfig | 58 +++++++++++++
include/configs/mx7ulp_com.h | 107 ++++++++++++++++++++++++
9 files changed, 382 insertions(+), 1 deletion(-)
create mode 100644 board/ea/mx7ulp_com/Kconfig
create mode 100644 board/ea/mx7ulp_com/MAINTAINERS
create mode 100644 board/ea/mx7ulp_com/Makefile
create mode 100644 board/ea/mx7ulp_com/imximage.cfg
create mode 100644 board/ea/mx7ulp_com/mx7ulp_com.c
create mode 100644 configs/mx7ulp_com_defconfig
create mode 100644 include/configs/mx7ulp_com.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 6a7dbb6309..c5c29dbcd0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -645,7 +645,8 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
imx7d-pico-hobbit.dtb
-dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
+dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
+ imx7ulp-evk.dtb
dtb-$(CONFIG_ARCH_IMX8) += \
fsl-imx8qm-apalis.dtb \
diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig
index 138c58363f..6680f856c5 100644
--- a/arch/arm/mach-imx/mx7ulp/Kconfig
+++ b/arch/arm/mach-imx/mx7ulp/Kconfig
@@ -15,6 +15,11 @@ choice
prompt "MX7ULP board select"
optional
+config TARGET_MX7ULP_COM
+ bool "Support MX7ULP COM board"
+ select MX7ULP
+ select SYS_ARCH_TIMER
+
config TARGET_MX7ULP_EVK
bool "Support mx7ulp EVK board"
select MX7ULP
@@ -22,6 +27,7 @@ config TARGET_MX7ULP_EVK
endchoice
+source "board/ea/mx7ulp_com/Kconfig"
source "board/freescale/mx7ulp_evk/Kconfig"
endif
diff --git a/board/ea/mx7ulp_com/Kconfig b/board/ea/mx7ulp_com/Kconfig
new file mode 100644
index 0000000000..90883aced4
--- /dev/null
+++ b/board/ea/mx7ulp_com/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX7ULP_COM
+
+config SYS_BOARD
+ default "mx7ulp_com"
+
+config SYS_VENDOR
+ default "ea"
+
+config SYS_CONFIG_NAME
+ default "mx7ulp_com"
+
+endif
diff --git a/board/ea/mx7ulp_com/MAINTAINERS b/board/ea/mx7ulp_com/MAINTAINERS
new file mode 100644
index 0000000000..3f69511b1a
--- /dev/null
+++ b/board/ea/mx7ulp_com/MAINTAINERS
@@ -0,0 +1,6 @@
+MX7ULPCOM BOARD
+M: Fabio Estevam <festevam@gmail.com>
+S: Maintained
+F: board/ea/mx7ulp_com/
+F: include/configs/mx7ulp_com.h
+F: configs/mx7ulp_com_defconfig
diff --git a/board/ea/mx7ulp_com/Makefile b/board/ea/mx7ulp_com/Makefile
new file mode 100644
index 0000000000..b3b230b172
--- /dev/null
+++ b/board/ea/mx7ulp_com/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx7ulp_com.o
diff --git a/board/ea/mx7ulp_com/imximage.cfg b/board/ea/mx7ulp_com/imximage.cfg
new file mode 100644
index 0000000000..e405d758b5
--- /dev/null
+++ b/board/ea/mx7ulp_com/imximage.cfg
@@ -0,0 +1,137 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx7ulp_evk/plugin.bin 0x2F020000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x403f00dc 0x00000000
+DATA 4 0x403e0040 0x01000020
+DATA 4 0x403e0500 0x01000000
+DATA 4 0x403e050c 0x80808080
+DATA 4 0x403e0508 0x00160002
+DATA 4 0x403E0510 0x00000001
+DATA 4 0x403E0514 0x00000014
+DATA 4 0x403e0500 0x00000001
+CHECK_BITS_SET 4 0x403e0500 0x01000000
+/*
+ * Default PFD0 divide is 27, which generates:
+ * PFD0 Freq = A7 APLL(528MHz) * 18 / 27 = 352MHz
+ *
+ * i.MX7ULP COM board can not run DDR at 352MHz, so
+ * use a divider of 30 (0x1E), which gives:
+ *
+ * PFD0 Freq = A7 APLL(528MHz) * 18 / 30 = 316.8MHz
+ */
+DATA 4 0x403e050c 0x8080801E
+CHECK_BITS_SET 4 0x403e050c 0x00000040
+DATA 4 0x403E0030 0x00000001
+DATA 4 0x403e0040 0x11000020
+DATA 4 0x403f00dc 0x42000000
+
+DATA 4 0x40B300AC 0x40000000
+
+DATA 4 0x40AD0128 0x00040000
+DATA 4 0x40AD00F8 0x00000000
+DATA 4 0x40AD00D8 0x00000180
+DATA 4 0x40AD0104 0x00000180
+DATA 4 0x40AD0108 0x00000180
+DATA 4 0x40AD0124 0x00010000
+DATA 4 0x40AD0080 0x0000018C
+DATA 4 0x40AD0084 0x0000018C
+DATA 4 0x40AD0088 0x0000018C
+DATA 4 0x40AD008C 0x0000018C
+
+DATA 4 0x40AD0120 0x00010000
+DATA 4 0x40AD010C 0x00000180
+DATA 4 0x40AD0110 0x00000180
+DATA 4 0x40AD0114 0x00000180
+DATA 4 0x40AD0118 0x00000180
+DATA 4 0x40AD0090 0x00000180
+DATA 4 0x40AD0094 0x00000180
+DATA 4 0x40AD0098 0x00000180
+DATA 4 0x40AD009C 0x00000180
+
+DATA 4 0x40AD00E0 0x00040000
+DATA 4 0x40AD00E4 0x00040000
+
+DATA 4 0x40AB001C 0x00008000
+DATA 4 0x40AB085C 0x0D3900A0
+DATA 4 0x40AB0800 0xA1390003
+DATA 4 0x40AB0890 0x00400000
+DATA 4 0x40AB081C 0x33333333
+DATA 4 0x40AB0820 0x33333333
+DATA 4 0x40AB0824 0x33333333
+DATA 4 0x40AB0828 0x33333333
+DATA 4 0x40AB08C0 0x24922492
+DATA 4 0x40AB0848 0x3A3E3838
+DATA 4 0x40AB0850 0x28282C2A
+DATA 4 0x40AB083C 0x20000000
+DATA 4 0x40AB0840 0x00000000
+DATA 4 0x40AB08B8 0x00000800
+DATA 4 0x40AB000C 0x292C40F5
+DATA 4 0x40AB0004 0x00020064
+DATA 4 0x40AB0010 0xB6AD0A83
+DATA 4 0x40AB0014 0x00C70093
+DATA 4 0x40AB0018 0x00211708
+DATA 4 0x40AB002C 0x0F9F26D2
+DATA 4 0x40AB0030 0x009F0E10
+DATA 4 0x40AB0038 0x00130556
+DATA 4 0x40AB0008 0x12272000
+DATA 4 0x40AB0040 0x0000003F
+DATA 4 0x40AB0000 0xC3110000
+DATA 4 0x40AB001C 0x00008010
+DATA 4 0x40AB001C 0x00008018
+DATA 4 0x40AB001C 0x003F8030
+DATA 4 0x40AB001C 0xFF0A8030
+DATA 4 0x40AB001C 0x82018030
+DATA 4 0x40AB001C 0x06028030
+DATA 4 0x40AB001C 0x01038030
+DATA 4 0x40AB001C 0x003F8038
+DATA 4 0x40AB001C 0xFF0A8038
+DATA 4 0x40AB001C 0x82018038
+DATA 4 0x40AB001C 0x06028038
+DATA 4 0x40AB001C 0x01038038
+DATA 4 0x40AB083C 0xA0000000
+DATA 4 0x40AB083C 0xA0000000
+DATA 4 0x40AB0020 0x00001800
+DATA 4 0x40AB0800 0xA1310003
+DATA 4 0x40AB001C 0x00000000
+#endif
diff --git a/board/ea/mx7ulp_com/mx7ulp_com.c b/board/ea/mx7ulp_com/mx7ulp_com.c
new file mode 100644
index 0000000000..6fc1631bf7
--- /dev/null
+++ b/board/ea/mx7ulp_com/mx7ulp_com.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mx7ulp-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_UP)
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+static iomux_cfg_t const lpuart4_pads[] = {
+ MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ mx7ulp_iomux_setup_multiple_pads(lpuart4_pads,
+ ARRAY_SIZE(lpuart4_pads));
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
diff --git a/configs/mx7ulp_com_defconfig b/configs/mx7ulp_com_defconfig
new file mode 100644
index 0000000000..44cae16fc8
--- /dev/null
+++ b/configs/mx7ulp_com_defconfig
@@ -0,0 +1,58 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7ULP=y
+CONFIG_SYS_TEXT_BASE=0x67800000
+CONFIG_LDO_ENABLED_MODE=y
+CONFIG_TARGET_MX7ULP_COM=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ea/mx7ulp_com/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx7ulp-com"
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-com"
+CONFIG_ENV_IS_IN_MMC=y
+# CONFIG_NET is not set
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_IMX_RGPIO2P=y
+# CONFIG_MXC_GPIO is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_ULP_WATCHDOG=y
diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h
new file mode 100644
index 0000000000..ba32afde38
--- /dev/null
+++ b/include/configs/mx7ulp_com.h
@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Embedded Artists i.MX7ULP COM board.
+ */
+
+#ifndef __MX7ULP_COM_CONFIG_H
+#define __MX7ULP_COM_CONFIG_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_BOARD_POSTCLK_INIT
+#define CONFIG_SYS_BOOTM_LEN 0x1000000
+
+#define SRC_BASE_ADDR CMC1_RBASE
+#define IRAM_BASE_ADDR OCRAM_0_BASE
+#define IOMUXC_BASE_ADDR IOMUXC1_RBASE
+
+/* Environment starts at 768k = 768 * 1024 = 786432 */
+#define CONFIG_ENV_OFFSET 786432
+/*
+ * Detect overlap between U-Boot image and environment area in build-time
+ *
+ * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot-dtb.imx offset
+ * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408
+ *
+ * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
+ * write the direct value here
+ */
+#define CONFIG_BOARD_SIZE_LIMIT 785408
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_MMCROOT "/dev/mmcblk0p2"
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+#define CONFIG_ENV_SIZE SZ_8K
+
+/* Using ULP WDOG for reset */
+#define WDOG_BASE_ADDR WDG1_RBASE
+
+#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */
+
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
+
+/* UART */
+#define LPUART_BASE LPUART4_RBASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Physical Memory Map */
+
+#define PHYS_SDRAM 0x60000000
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+
+#define CONFIG_LOADADDR 0x60800000
+
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_512M)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "image=zImage\0" \
+ "console=ttyLP0\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=imx7ulp-com.dtb\0" \
+ "fdt_addr=0x63000000\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "fi;\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "fi; " \
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+#define CONFIG_CMD_CACHE
+#endif
+
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#endif /* __CONFIG_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v2 6/6] mx7ulp: Add support for Embedded Artists COM board
2019-10-30 13:41 ` [U-Boot] [PATCH v2 6/6] mx7ulp: Add support for Embedded Artists COM board Fabio Estevam
@ 2019-11-05 5:57 ` Peng Fan
2019-11-05 12:49 ` Fabio Estevam
0 siblings, 1 reply; 8+ messages in thread
From: Peng Fan @ 2019-11-05 5:57 UTC (permalink / raw)
To: u-boot
> Subject: [PATCH v2 6/6] mx7ulp: Add support for Embedded Artists COM
> board
Hi Fabio,
Seems you not add dts files. CI build fail
arm: + mx7ulp_com
+make[3]: *** No rule to make target 'arch/arm/dts/imx7ulp-com.dtb', needed by 'dtbs'. Stop.
+make[2]: *** [arch-dtbs] Error 2
+make[1]: *** [dts/dt.dtb] Error 2
+make: *** [sub-make] Error 2
Thanks,
Peng.
>
> The Embedded Artists COM board is based on NXP i.MX7ULP.
>
> It has a BD70528 PMIC from Rohm with discrete DCDC powering option and
> improved current observability (compared to the existing NXP i.MX7ULP EVK).
>
> Add the initial support for the board.
>
> Signed-off-by: Fabio Estevam <festevam@gmail.com>
> ---
> Changes since v1:
> - Lower the DDR frequency inside DCD as it is safer (Ye Li)
> - Drop CONFIG_IMX7ULP_LOWER_DDR_FREQUENCY=y
>
> arch/arm/dts/Makefile | 3 +-
> arch/arm/mach-imx/mx7ulp/Kconfig | 6 ++
> board/ea/mx7ulp_com/Kconfig | 12 +++
> board/ea/mx7ulp_com/MAINTAINERS | 6 ++
> board/ea/mx7ulp_com/Makefile | 6 ++
> board/ea/mx7ulp_com/imximage.cfg | 137
> +++++++++++++++++++++++++++++++
> board/ea/mx7ulp_com/mx7ulp_com.c | 48 +++++++++++
> configs/mx7ulp_com_defconfig | 58 +++++++++++++
> include/configs/mx7ulp_com.h | 107 ++++++++++++++++++++++++
> 9 files changed, 382 insertions(+), 1 deletion(-) create mode 100644
> board/ea/mx7ulp_com/Kconfig create mode 100644
> board/ea/mx7ulp_com/MAINTAINERS create mode 100644
> board/ea/mx7ulp_com/Makefile create mode 100644
> board/ea/mx7ulp_com/imximage.cfg create mode 100644
> board/ea/mx7ulp_com/mx7ulp_com.c create mode 100644
> configs/mx7ulp_com_defconfig create mode 100644
> include/configs/mx7ulp_com.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
> 6a7dbb6309..c5c29dbcd0 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -645,7 +645,8 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
> imx7d-pico-hobbit.dtb
>
>
> -dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
> +dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
> + imx7ulp-evk.dtb
>
> dtb-$(CONFIG_ARCH_IMX8) += \
> fsl-imx8qm-apalis.dtb \
> diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig
> b/arch/arm/mach-imx/mx7ulp/Kconfig
> index 138c58363f..6680f856c5 100644
> --- a/arch/arm/mach-imx/mx7ulp/Kconfig
> +++ b/arch/arm/mach-imx/mx7ulp/Kconfig
> @@ -15,6 +15,11 @@ choice
> prompt "MX7ULP board select"
> optional
>
> +config TARGET_MX7ULP_COM
> + bool "Support MX7ULP COM board"
> + select MX7ULP
> + select SYS_ARCH_TIMER
> +
> config TARGET_MX7ULP_EVK
> bool "Support mx7ulp EVK board"
> select MX7ULP
> @@ -22,6 +27,7 @@ config TARGET_MX7ULP_EVK
>
> endchoice
>
> +source "board/ea/mx7ulp_com/Kconfig"
> source "board/freescale/mx7ulp_evk/Kconfig"
>
> endif
> diff --git a/board/ea/mx7ulp_com/Kconfig b/board/ea/mx7ulp_com/Kconfig
> new file mode 100644 index 0000000000..90883aced4
> --- /dev/null
> +++ b/board/ea/mx7ulp_com/Kconfig
> @@ -0,0 +1,12 @@
> +if TARGET_MX7ULP_COM
> +
> +config SYS_BOARD
> + default "mx7ulp_com"
> +
> +config SYS_VENDOR
> + default "ea"
> +
> +config SYS_CONFIG_NAME
> + default "mx7ulp_com"
> +
> +endif
> diff --git a/board/ea/mx7ulp_com/MAINTAINERS
> b/board/ea/mx7ulp_com/MAINTAINERS new file mode 100644 index
> 0000000000..3f69511b1a
> --- /dev/null
> +++ b/board/ea/mx7ulp_com/MAINTAINERS
> @@ -0,0 +1,6 @@
> +MX7ULPCOM BOARD
> +M: Fabio Estevam <festevam@gmail.com>
> +S: Maintained
> +F: board/ea/mx7ulp_com/
> +F: include/configs/mx7ulp_com.h
> +F: configs/mx7ulp_com_defconfig
> diff --git a/board/ea/mx7ulp_com/Makefile
> b/board/ea/mx7ulp_com/Makefile new file mode 100644 index
> 0000000000..b3b230b172
> --- /dev/null
> +++ b/board/ea/mx7ulp_com/Makefile
> @@ -0,0 +1,6 @@
> +# (C) Copyright 2016 Freescale Semiconductor, Inc.
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y := mx7ulp_com.o
> diff --git a/board/ea/mx7ulp_com/imximage.cfg
> b/board/ea/mx7ulp_com/imximage.cfg
> new file mode 100644
> index 0000000000..e405d758b5
> --- /dev/null
> +++ b/board/ea/mx7ulp_com/imximage.cfg
> @@ -0,0 +1,137 @@
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + *
> + * Refer docs/README.imxmage for more details about how-to configure
> + * and create imximage boot image
> + *
> + * The syntax is taken as close as possible with the kwbimage */
> +
> +#define __ASSEMBLY__
> +#include <config.h>
> +
> +/* image version */
> +
> +IMAGE_VERSION 2
> +
> +/*
> + * Boot Device : one of
> + * spi/sd/nand/onenand, qspi/nor
> + */
> +
> +BOOT_FROM sd
> +
> +#ifdef CONFIG_USE_IMXIMG_PLUGIN
> +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
> +PLUGIN board/freescale/mx7ulp_evk/plugin.bin 0x2F020000
> +#else
> +
> +#ifdef CONFIG_SECURE_BOOT
> +CSF CONFIG_CSF_SIZE
> +#endif
> +/*
> + * Device Configuration Data (DCD)
> + *
> + * Each entry must have the format:
> + * Addr-type Address Value
> + *
> + * where:
> + * Addr-type register length (1,2 or 4 bytes)
> + * Address absolute address of the register
> + * value value to be stored in the register
> + */
> +DATA 4 0x403f00dc 0x00000000
> +DATA 4 0x403e0040 0x01000020
> +DATA 4 0x403e0500 0x01000000
> +DATA 4 0x403e050c 0x80808080
> +DATA 4 0x403e0508 0x00160002
> +DATA 4 0x403E0510 0x00000001
> +DATA 4 0x403E0514 0x00000014
> +DATA 4 0x403e0500 0x00000001
> +CHECK_BITS_SET 4 0x403e0500 0x01000000
> +/*
> + * Default PFD0 divide is 27, which generates:
> + * PFD0 Freq = A7 APLL(528MHz) * 18 / 27 = 352MHz
> + *
> + * i.MX7ULP COM board can not run DDR at 352MHz, so
> + * use a divider of 30 (0x1E), which gives:
> + *
> + * PFD0 Freq = A7 APLL(528MHz) * 18 / 30 = 316.8MHz */
> +DATA 4 0x403e050c 0x8080801E
> +CHECK_BITS_SET 4 0x403e050c 0x00000040
> +DATA 4 0x403E0030 0x00000001
> +DATA 4 0x403e0040 0x11000020
> +DATA 4 0x403f00dc 0x42000000
> +
> +DATA 4 0x40B300AC 0x40000000
> +
> +DATA 4 0x40AD0128 0x00040000
> +DATA 4 0x40AD00F8 0x00000000
> +DATA 4 0x40AD00D8 0x00000180
> +DATA 4 0x40AD0104 0x00000180
> +DATA 4 0x40AD0108 0x00000180
> +DATA 4 0x40AD0124 0x00010000
> +DATA 4 0x40AD0080 0x0000018C
> +DATA 4 0x40AD0084 0x0000018C
> +DATA 4 0x40AD0088 0x0000018C
> +DATA 4 0x40AD008C 0x0000018C
> +
> +DATA 4 0x40AD0120 0x00010000
> +DATA 4 0x40AD010C 0x00000180
> +DATA 4 0x40AD0110 0x00000180
> +DATA 4 0x40AD0114 0x00000180
> +DATA 4 0x40AD0118 0x00000180
> +DATA 4 0x40AD0090 0x00000180
> +DATA 4 0x40AD0094 0x00000180
> +DATA 4 0x40AD0098 0x00000180
> +DATA 4 0x40AD009C 0x00000180
> +
> +DATA 4 0x40AD00E0 0x00040000
> +DATA 4 0x40AD00E4 0x00040000
> +
> +DATA 4 0x40AB001C 0x00008000
> +DATA 4 0x40AB085C 0x0D3900A0
> +DATA 4 0x40AB0800 0xA1390003
> +DATA 4 0x40AB0890 0x00400000
> +DATA 4 0x40AB081C 0x33333333
> +DATA 4 0x40AB0820 0x33333333
> +DATA 4 0x40AB0824 0x33333333
> +DATA 4 0x40AB0828 0x33333333
> +DATA 4 0x40AB08C0 0x24922492
> +DATA 4 0x40AB0848 0x3A3E3838
> +DATA 4 0x40AB0850 0x28282C2A
> +DATA 4 0x40AB083C 0x20000000
> +DATA 4 0x40AB0840 0x00000000
> +DATA 4 0x40AB08B8 0x00000800
> +DATA 4 0x40AB000C 0x292C40F5
> +DATA 4 0x40AB0004 0x00020064
> +DATA 4 0x40AB0010 0xB6AD0A83
> +DATA 4 0x40AB0014 0x00C70093
> +DATA 4 0x40AB0018 0x00211708
> +DATA 4 0x40AB002C 0x0F9F26D2
> +DATA 4 0x40AB0030 0x009F0E10
> +DATA 4 0x40AB0038 0x00130556
> +DATA 4 0x40AB0008 0x12272000
> +DATA 4 0x40AB0040 0x0000003F
> +DATA 4 0x40AB0000 0xC3110000
> +DATA 4 0x40AB001C 0x00008010
> +DATA 4 0x40AB001C 0x00008018
> +DATA 4 0x40AB001C 0x003F8030
> +DATA 4 0x40AB001C 0xFF0A8030
> +DATA 4 0x40AB001C 0x82018030
> +DATA 4 0x40AB001C 0x06028030
> +DATA 4 0x40AB001C 0x01038030
> +DATA 4 0x40AB001C 0x003F8038
> +DATA 4 0x40AB001C 0xFF0A8038
> +DATA 4 0x40AB001C 0x82018038
> +DATA 4 0x40AB001C 0x06028038
> +DATA 4 0x40AB001C 0x01038038
> +DATA 4 0x40AB083C 0xA0000000
> +DATA 4 0x40AB083C 0xA0000000
> +DATA 4 0x40AB0020 0x00001800
> +DATA 4 0x40AB0800 0xA1310003
> +DATA 4 0x40AB001C 0x00000000
> +#endif
> diff --git a/board/ea/mx7ulp_com/mx7ulp_com.c
> b/board/ea/mx7ulp_com/mx7ulp_com.c
> new file mode 100644
> index 0000000000..6fc1631bf7
> --- /dev/null
> +++ b/board/ea/mx7ulp_com/mx7ulp_com.c
> @@ -0,0 +1,48 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/arch/mx7ulp-pins.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/gpio.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_PAD_CTRL (PAD_CTL_PUS_UP)
> +
> +int dram_init(void)
> +{
> + gd->ram_size = imx_ddr_size();
> +
> + return 0;
> +}
> +
> +static iomux_cfg_t const lpuart4_pads[] = {
> + MX7ULP_PAD_PTC3__LPUART4_RX |
> MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX7ULP_PAD_PTC2__LPUART4_TX |
> MUX_PAD_CTRL(UART_PAD_CTRL), };
> +
> +static void setup_iomux_uart(void)
> +{
> + mx7ulp_iomux_setup_multiple_pads(lpuart4_pads,
> + ARRAY_SIZE(lpuart4_pads));
> +}
> +
> +int board_early_init_f(void)
> +{
> + setup_iomux_uart();
> +
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + /* address of boot parameters */
> + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> +
> + return 0;
> +}
> diff --git a/configs/mx7ulp_com_defconfig b/configs/mx7ulp_com_defconfig
> new file mode 100644 index 0000000000..44cae16fc8
> --- /dev/null
> +++ b/configs/mx7ulp_com_defconfig
> @@ -0,0 +1,58 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_MX7ULP=y
> +CONFIG_SYS_TEXT_BASE=0x67800000
> +CONFIG_LDO_ENABLED_MODE=y
> +CONFIG_TARGET_MX7ULP_COM=y
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ea/mx7ulp_com/imxi
> mage.cfg"
> +CONFIG_DEFAULT_FDT_FILE="imx7ulp-com"
> +CONFIG_BOUNCE_BUFFER=y
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_CMD_BOOTZ=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_READ=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_USB_MASS_STORAGE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-com"
> +CONFIG_ENV_IS_IN_MMC=y
> +# CONFIG_NET is not set
> +CONFIG_DM=y
> +CONFIG_DM_GPIO=y
> +CONFIG_IMX_RGPIO2P=y
> +# CONFIG_MXC_GPIO is not set
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_IMX_LPI2C=y
> +CONFIG_DM_MMC=y
> +CONFIG_FSL_USDHC=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SF_DEFAULT_MODE=0
> +CONFIG_SF_DEFAULT_SPEED=40000000
> +CONFIG_SPI_FLASH_ATMEL=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_IMX7ULP=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_DM_SERIAL=y
> +CONFIG_FSL_LPUART=y
> +CONFIG_SPI=y
> +CONFIG_DM_SPI=y
> +CONFIG_FSL_QSPI=y
> +CONFIG_USB=y
> +CONFIG_DM_USB=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_STORAGE=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GADGET_MANUFACTURER="FSL"
> +CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> +CONFIG_CI_UDC=y
> +CONFIG_USB_GADGET_DOWNLOAD=y
> +CONFIG_ULP_WATCHDOG=y
> diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h
> new file mode 100644 index 0000000000..ba32afde38
> --- /dev/null
> +++ b/include/configs/mx7ulp_com.h
> @@ -0,0 +1,107 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + *
> + * Configuration settings for the Embedded Artists i.MX7ULP COM board.
> + */
> +
> +#ifndef __MX7ULP_COM_CONFIG_H
> +#define __MX7ULP_COM_CONFIG_H
> +
> +#include <linux/sizes.h>
> +#include <asm/arch/imx-regs.h>
> +
> +#define CONFIG_BOARD_POSTCLK_INIT
> +#define CONFIG_SYS_BOOTM_LEN 0x1000000
> +
> +#define SRC_BASE_ADDR CMC1_RBASE
> +#define IRAM_BASE_ADDR OCRAM_0_BASE
> +#define IOMUXC_BASE_ADDR IOMUXC1_RBASE
> +
> +/* Environment starts at 768k = 768 * 1024 = 786432 */
> +#define CONFIG_ENV_OFFSET 786432
> +/*
> + * Detect overlap between U-Boot image and environment area in
> +build-time
> + *
> + * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot-dtb.imx
> offset
> + * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408
> + *
> + * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
> + * write the direct value here
> + */
> +#define CONFIG_BOARD_SIZE_LIMIT 785408
> +#define CONFIG_SYS_MMC_ENV_DEV 0
> +#define CONFIG_MMCROOT "/dev/mmcblk0p2"
> +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
> +
> +#define CONFIG_ENV_SIZE SZ_8K
> +
> +/* Using ULP WDOG for reset */
> +#define WDOG_BASE_ADDR WDG1_RBASE
> +
> +#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR
> */
> +
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_SETUP_MEMORY_TAGS
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
> +
> +/* UART */
> +#define LPUART_BASE LPUART4_RBASE
> +
> +/* allow to overwrite serial and ethaddr */ #define
> +CONFIG_ENV_OVERWRITE
> +
> +/* Physical Memory Map */
> +
> +#define PHYS_SDRAM 0x60000000
> +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
> +
> +#define CONFIG_LOADADDR 0x60800000
> +
> +#define CONFIG_SYS_MEMTEST_END
> (CONFIG_SYS_MEMTEST_START + SZ_512M)
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "image=zImage\0" \
> + "console=ttyLP0\0" \
> + "fdt_high=0xffffffff\0" \
> + "initrd_high=0xffffffff\0" \
> + "fdt_file=imx7ulp-com.dtb\0" \
> + "fdt_addr=0x63000000\0" \
> + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> + "mmcargs=setenv bootargs console=${console},${baudrate} " \
> + "root=${mmcroot}\0" \
> + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> ${image}\0" \
> + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0"
> \
> + "mmcboot=echo Booting from mmc ...; " \
> + "run mmcargs; " \
> + "if run loadfdt; then " \
> + "bootz ${loadaddr} - ${fdt_addr}; " \
> + "fi;\0" \
> +
> +#define CONFIG_BOOTCOMMAND \
> + "if run loadimage; then " \
> + "run mmcboot; " \
> + "fi; " \
> +
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +
> +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
> +#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define
> +CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
> +#define CONFIG_CMD_CACHE
> +#endif
> +
> +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI |
> PORT_PTS_PTW)
> +#endif /* __CONFIG_H */
> --
> 2.17.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v2 6/6] mx7ulp: Add support for Embedded Artists COM board
2019-11-05 5:57 ` Peng Fan
@ 2019-11-05 12:49 ` Fabio Estevam
0 siblings, 0 replies; 8+ messages in thread
From: Fabio Estevam @ 2019-11-05 12:49 UTC (permalink / raw)
To: u-boot
Hi Peng,
On Tue, Nov 5, 2019 at 2:57 AM Peng Fan <peng.fan@nxp.com> wrote:
> Hi Fabio,
>
> Seems you not add dts files. CI build fail
> arm: + mx7ulp_com
> +make[3]: *** No rule to make target 'arch/arm/dts/imx7ulp-com.dtb', needed by 'dtbs'. Stop.
> +make[2]: *** [arch-dtbs] Error 2
> +make[1]: *** [dts/dt.dtb] Error 2
> +make: *** [sub-make] Error 2
Ops, sorry. I have sent a v3 which adds the dtb.
Thanks
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-11-05 12:49 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-10-30 13:41 [U-Boot] [PATCH v2 1/6] mx7ulp: Print the LDO mode status Fabio Estevam
2019-10-30 13:41 ` [U-Boot] [PATCH v2 2/6] mx7ulp: Introduce the CONFIG_LDO_ENABLED_MODE option Fabio Estevam
2019-10-30 13:41 ` [U-Boot] [PATCH v2 3/6] mx7ulp: Remove the _RUN notation from the PMC1 LDOVL definitions Fabio Estevam
2019-10-30 13:41 ` [U-Boot] [PATCH v2 4/6] mx7ulp: scg: Remove unnused scg_a7_apll_init() Fabio Estevam
2019-10-30 13:41 ` [U-Boot] [PATCH v2 5/6] mx7ulp: Sync the device tree related files Fabio Estevam
2019-10-30 13:41 ` [U-Boot] [PATCH v2 6/6] mx7ulp: Add support for Embedded Artists COM board Fabio Estevam
2019-11-05 5:57 ` Peng Fan
2019-11-05 12:49 ` Fabio Estevam
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