From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/2] ARM: socfpga: Actually put bridges into reset on Gen5 in bridge disable
Date: Wed, 20 Nov 2019 22:34:30 +0100 [thread overview]
Message-ID: <20191120213431.18111-1-marex@denx.de> (raw)
On Gen5, the 'bridge disable' command write 0x0 to brgmodrst register,
which releases all bridges from reset, instead of putting all bridges
into reset. Fix this by inverting the mask and actually putting the
bridges into reset.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
---
arch/arm/mach-socfpga/misc_gen5.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 31681b799d..36f00aee31 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -231,7 +231,7 @@ void do_bridge_reset(int enable, unsigned int mask)
} else {
writel(0, &sysmgr_regs->fpgaintfgrp_module);
writel(0, &sdr_ctrl->fpgaport_rst);
- writel(0, &reset_manager_base->brg_mod_reset);
+ writel(0x7, &reset_manager_base->brg_mod_reset);
writel(1, &nic301_regs->remap);
}
}
--
2.24.0.432.g9d3f5f5b63
next reply other threads:[~2019-11-20 21:34 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-20 21:34 Marek Vasut [this message]
2019-11-20 21:34 ` [U-Boot] [PATCH 2/2] ARM: socfpga: Purge pending transactions upon enabling bridges on Gen5 Marek Vasut
2019-11-21 9:59 ` Tan, Ley Foon
2019-11-21 10:17 ` Marek Vasut
2019-11-21 9:56 ` [U-Boot] [PATCH 1/2] ARM: socfpga: Actually put bridges into reset on Gen5 in bridge disable Tan, Ley Foon
2019-11-21 10:26 ` Simon Goldschmidt
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