From mboxrd@z Thu Jan 1 00:00:00 1970 From: Anand Moon Date: Tue, 26 Nov 2019 21:12:03 +0000 Subject: [U-Boot] [PATCH 1/4] mmc: meson-gx: Fix tx phase in the tuning process In-Reply-To: <20191126211206.4537-1-linux.amoon@gmail.com> References: <20191126211206.4537-1-linux.amoon@gmail.com> Message-ID: <20191126211206.4537-2-linux.amoon@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de odroid n2 eMMC module would failed to boot up, because of TX phase clk failure, fix the typo in TX phase macro to help tune correct clk freqency. Before these changes. clock is enabled (380953Hz) clock is enabled (25000000Hz) after these changes clock is enabled (380953Hz) clock is enabled (25000000Hz) clock is enabled (52000000Hz) clock is enabled (52000000Hz) clock is enabled (52000000Hz) Signed-off-by: Anand Moon --- Tested on new orange - eMMC AJNB4R 14.6 GiB MMC 5.1 old back - eMMC CGND3R 58.2 GiB MMC 5.0 --- drivers/mmc/meson_gx_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 031cc79ccb..87bea2888b 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -53,7 +53,7 @@ static void meson_mmc_config_clock(struct mmc *mmc) meson_mmc_clk |= CLK_CO_PHASE_180; /* 180 phase tx clock */ - meson_mmc_clk |= CLK_TX_PHASE_000; + meson_mmc_clk |= CLK_TX_PHASE_180; /* clock settings */ meson_mmc_clk |= clk_src; -- 2.24.0