From mboxrd@z Thu Jan 1 00:00:00 1970 From: Igor Opaniuk Date: Thu, 28 Nov 2019 15:56:20 +0200 Subject: [U-Boot] [PATCH v2 2/3] mach-imx: bootaux: add dcache flushing before enabling M4 In-Reply-To: <20191128135621.12719-1-igor.opaniuk@gmail.com> References: <20191128135621.12719-1-igor.opaniuk@gmail.com> Message-ID: <20191128135621.12719-2-igor.opaniuk@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Igor Opaniuk This patch fixes the issue with broken bootaux command, when M4 binary is loaded and data cache isn't flushed before M4 core is enabled. Reproducing: > tftpboot ${loadaddr} ${board_name}/hello_world.bin > cp.b ${loadaddr} 0x7F8000 $filesize > bootaux 0x7F8000 Signed-off-by: Igor Opaniuk --- arch/arm/mach-imx/imx_bootaux.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index ee786f7d06..c750cee60c 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -27,6 +27,8 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) writel(stack, M4_BOOTROM_BASE_ADDR); writel(pc, M4_BOOTROM_BASE_ADDR + 4); + flush_dcache_all(); + /* Enable M4 */ #ifdef CONFIG_IMX8M call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0); -- 2.17.1