From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jagan Teki Date: Mon, 30 Dec 2019 17:34:07 +0530 Subject: [PATCH 6/8] ARM: dts: imx6q-icore-mipi: Use 1.5 version of i.Core MX6DL In-Reply-To: <20191230120409.884-1-jagan@amarulasolutions.com> References: <20191230120409.884-1-jagan@amarulasolutions.com> Message-ID: <20191230120409.884-7-jagan@amarulasolutions.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de The EDIMM STARTER KIT i.Core 1.5 MIPI Evaluation is based on the 1.5 version of the i.Core MX6 cpu module. The 1.5 version differs from the original one for a few details, including the ethernet PHY interface clock provider. With this commit, the ethernet interface works properly: SMSC LAN8710/LAN8720 2188000.ethernet-1:00: attached PHY driver While before using the 1.5 version, ethernet failed to startup do to un-clocked PHY interface: fec 2188000.ethernet eth0: could not attach to PHY Similar fix has merged for i.Core MX6Q but missed to update for DL. Signed-off-by: Michael Trimarchi Signed-off-by: Jagan Teki --- arch/arm/dts/imx6dl-icore-mipi.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/imx6dl-icore-mipi.dts b/arch/arm/dts/imx6dl-icore-mipi.dts index e43bccb78a..d8f3821a0f 100644 --- a/arch/arm/dts/imx6dl-icore-mipi.dts +++ b/arch/arm/dts/imx6dl-icore-mipi.dts @@ -8,7 +8,7 @@ /dts-v1/; #include "imx6dl.dtsi" -#include "imx6qdl-icore.dtsi" +#include "imx6qdl-icore-1.5.dtsi" / { model = "Engicam i.CoreM6 DualLite/Solo MIPI Starter Kit"; -- 2.18.0.321.gffc6fa0e3