* [PATCH v2 1/8] ARM: MediaTek: Add support for MediaTek MT8512 SoC
2019-12-31 3:29 [PATCH v2 0/8] Add support for MediaTek MT8512 Soc mingming lee
@ 2019-12-31 3:29 ` mingming lee
2020-01-16 14:41 ` Tom Rini
2019-12-31 3:29 ` [PATCH v2 2/8] clk: mediatek: add driver support for MT8512 mingming lee
` (6 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: mingming lee @ 2019-12-31 3:29 UTC (permalink / raw)
To: u-boot
Add support for MediaTek MT8512 SoC. This include the file
that will initialize the SoC after boot and its device tree.
Signed-off-by: mingming lee <mingming.lee@mediatek.com>
---
Changes for v2:
-Sort device nodes reg address order and alphabetically.
---
arch/arm/dts/mt8512.dtsi | 115 ++++++++++++++++++
arch/arm/mach-mediatek/Kconfig | 15 +++
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt8512/Makefile | 4 +
arch/arm/mach-mediatek/mt8512/init.c | 78 ++++++++++++
arch/arm/mach-mediatek/mt8512/lowlevel_init.S | 32 +++++
6 files changed, 245 insertions(+)
create mode 100644 arch/arm/dts/mt8512.dtsi
create mode 100644 arch/arm/mach-mediatek/mt8512/Makefile
create mode 100644 arch/arm/mach-mediatek/mt8512/init.c
create mode 100644 arch/arm/mach-mediatek/mt8512/lowlevel_init.S
diff --git a/arch/arm/dts/mt8512.dtsi b/arch/arm/dts/mt8512.dtsi
new file mode 100644
index 0000000000..01a02a7ebf
--- /dev/null
+++ b/arch/arm/dts/mt8512.dtsi
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ *
+ */
+
+#include <dt-bindings/clock/mt8512-clk.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "mediatek,mt8512";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gic: interrupt-controller at c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0xc000000 0x40000>, /* GICD */
+ <0xc080000 0x200000>; /* GICR */
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ topckgen: clock-controller at 10000000 {
+ compatible = "mediatek,mt8512-topckgen";
+ reg = <0x10000000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ topckgen_cg: clock-controller-cg at 10000000 {
+ compatible = "mediatek,mt8512-topckgen-cg";
+ reg = <0x10000000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: clock-controller at 10001000 {
+ compatible = "mediatek,mt8512-infracfg";
+ reg = <0x10001000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pinctrl: pinctrl at 10005000 {
+ compatible = "mediatek,mt8512-pinctrl";
+ reg = <0x10005000 0x1000>;
+ gpio: gpio-controller {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ watchdog0: watchdog at 10007000 {
+ compatible = "mediatek,wdt";
+ reg = <0x10007000 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_FALLING>;
+ #reset-cells = <1>;
+ status = "disabled";
+ timeout-sec = <60>;
+ reset-on-timeout;
+ };
+
+ timer0: apxgpt at 10008000 {
+ compatible = "mediatek,timer";
+ reg = <0x10008000 0x1000>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYS_26M_D2>,
+ <&topckgen CLK_TOP_CLK32K>,
+ <&infracfg CLK_INFRA_APXGPT>;
+ clock-names = "clk13m",
+ "clk32k",
+ "bus";
+ };
+
+ apmixedsys: clock-controller at 1000c000 {
+ compatible = "mediatek,mt8512-apmixedsys";
+ reg = <0x1000c000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ sysirq: interrupt-controller at 10200a80 {
+ compatible = "mediatek,sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0x10200a80 0x50>;
+ };
+
+ uart0: serial at 11002000 {
+ compatible = "mediatek,hsuart";
+ reg = <0x11002000 0x1000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_CLK26M>,
+ <&infracfg CLK_INFRA_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ mmc0: mmc at 11230000 {
+ compatible = "mediatek,mt8512-mmc";
+ reg = <0x11230000 0x1000>,
+ <0x11cd0000 0x1000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+ <&infracfg CLK_INFRA_MSDC0>,
+ <&infracfg CLK_INFRA_MSDC0_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+};
\ No newline at end of file
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index ad453a60c1..bca88b8db8 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -6,6 +6,10 @@ config SYS_SOC
config SYS_VENDOR
default "mediatek"
+config MT8512
+ bool "MediaTek MT8512 SoC"
+ default n
+
choice
prompt "MediaTek board select"
@@ -29,6 +33,16 @@ config TARGET_MT7629
including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
+config TARGET_MT8512
+ bool "MediaTek MT8512 M1 Board"
+ select ARM64
+ select MT8512
+ help
+ The MediaTek MT8512 is a ARM64-based SoC with a quad-core Cortex-A53.
+ including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM,
+ Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo
+ chip and several DDR3 and DDR4 options.
+
config TARGET_MT8516
bool "MediaTek MT8516 SoC"
select ARM64
@@ -51,6 +65,7 @@ endchoice
source "board/mediatek/mt7623/Kconfig"
source "board/mediatek/mt7629/Kconfig"
+source "board/mediatek/mt8512/Kconfig"
source "board/mediatek/mt8518/Kconfig"
source "board/mediatek/pumpkin/Kconfig"
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index b9b2355e03..6129ac88ab 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -3,6 +3,7 @@
obj-y += cpu.o
obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_MT8512) += mt8512/
obj-$(CONFIG_TARGET_MT7623) += mt7623/
obj-$(CONFIG_TARGET_MT7629) += mt7629/
obj-$(CONFIG_TARGET_MT8516) += mt8516/
diff --git a/arch/arm/mach-mediatek/mt8512/Makefile b/arch/arm/mach-mediatek/mt8512/Makefile
new file mode 100644
index 0000000000..007eb4a367
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8512/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
+obj-y += lowlevel_init.o
diff --git a/arch/arm/mach-mediatek/mt8512/init.c b/arch/arm/mach-mediatek/mt8512/init.c
new file mode 100644
index 0000000000..a38b5d12d9
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8512/init.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Configuration for MediaTek MT8512 SoC
+ *
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <ram.h>
+#include <wdt.h>
+#include <asm/arch/misc.h>
+#include <asm/armv8/mmu.h>
+#include <asm/sections.h>
+#include <dm/uclass.h>
+#include <dt-bindings/clock/mt8512-clk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+phys_size_t get_effective_memsize(void)
+{
+ /* limit stack below tee reserve memory */
+ return gd->ram_size - 6 * SZ_1M;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = gd->ram_base;
+ gd->bd->bi_dram[0].size = get_effective_memsize();
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ struct udevice *watchdog_dev = NULL;
+
+ if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev))
+ if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev))
+ psci_system_reset();
+
+ wdt_expire_now(watchdog_dev, 0);
+}
+
+int print_cpuinfo(void)
+{
+ debug("CPU: MediaTek MT8512\n");
+ return 0;
+}
+
+static struct mm_region mt8512_mem_map[] = {
+ {
+ /* DDR */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+ }, {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ 0,
+ }
+};
+
+struct mm_region *mem_map = mt8512_mem_map;
diff --git a/arch/arm/mach-mediatek/mt8512/lowlevel_init.S b/arch/arm/mach-mediatek/mt8512/lowlevel_init.S
new file mode 100644
index 0000000000..ad392120f4
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8512/lowlevel_init.S
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+/*
+ * Switch from AArch64 EL2 to AArch32 EL2
+ * @param inputs:
+ * x0: argument, zero
+ * x1: machine nr
+ * x2: fdt address
+ * x3: input argument
+ * x4: kernel entry point
+ * @param outputs for secure firmware:
+ * x0: function id
+ * x1: kernel entry point
+ * x2: machine nr
+ * x3: fdt address
+*/
+.global armv8_el2_to_aarch32
+armv8_el2_to_aarch32:
+ mov x3, x2
+ mov x2, x1
+ mov x1, x4
+ mov x4, #0
+ /* Define in src\bsp\trustzone\atf\v1.2\ */
+ /* mt8xxx\plat\mediatek\common\sip_svc.h */
+ /* MTK_SIP_KERNEL_BOOT_AARCH64 for U-BOOT-64 to KERNEL*/
+ ldr x0, =0xC2000200
+ SMC #0
+ ret
--
2.24.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 2/8] clk: mediatek: add driver support for MT8512
2019-12-31 3:29 [PATCH v2 0/8] Add support for MediaTek MT8512 Soc mingming lee
2019-12-31 3:29 ` [PATCH v2 1/8] ARM: MediaTek: Add support for MediaTek MT8512 SoC mingming lee
@ 2019-12-31 3:29 ` mingming lee
2020-01-16 14:41 ` Tom Rini
2019-12-31 3:29 ` [PATCH v2 3/8] clk: mediatek: add set_clr_upd mux type flow mingming lee
` (5 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: mingming lee @ 2019-12-31 3:29 UTC (permalink / raw)
To: u-boot
Add clock driver for MediaTek MT8512 SoC, include topckgen,
apmixedsys and infracfg support.
Signed-off-by: mingming lee <mingming.lee@mediatek.com>
---
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8512.c | 873 +++++++++++++++++++++++++
include/dt-bindings/clock/mt8512-clk.h | 197 ++++++
3 files changed, 1071 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8512.c
create mode 100644 include/dt-bindings/clock/mt8512-clk.h
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index e92bcd4efe..b82243885c 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -3,6 +3,7 @@
obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
# SoC Drivers
+obj-$(CONFIG_MT8512) += clk-mt8512.o
obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c
new file mode 100644
index 0000000000..cb168f146b
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8512.c
@@ -0,0 +1,873 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8512 SoC
+ *
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Chen Zhong <chen.zhong@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt8512-clk.h>
+
+#include "clk-mtk.h"
+
+#define MT8512_PLL_FMAX (3800UL * MHZ)
+#define MT8512_PLL_FMIN (1500UL * MHZ)
+#define MT8512_CON0_RST_BAR BIT(23)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift, _pcw_chg_reg) { \
+ .id = _id, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .rst_bar_mask = MT8512_CON0_RST_BAR, \
+ .fmax = MT8512_PLL_FMAX, \
+ .fmin = MT8512_PLL_FMIN, \
+ .flags = _flags, \
+ .pcwbits = _pcwbits, \
+ .pcwibits = 8, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ .pcw_chg_reg = _pcw_chg_reg, \
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001,
+ 0, 22, 0x0310, 24, 0x0310, 0, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0x00000001,
+ HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, 0),
+ PLL(CLK_APMIXED_UNIVPLL2, 0x0208, 0x0214, 0x00000001,
+ HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, 0),
+ PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001,
+ 0, 22, 0x0354, 24, 0x0354, 0, 0),
+ PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001,
+ 0, 32, 0x0320, 24, 0x0324, 0, 0x0320),
+ PLL(CLK_APMIXED_APLL2, 0x0360, 0x0370, 0x00000001,
+ 0, 32, 0x0364, 24, 0x0368, 0, 0x0364),
+ PLL(CLK_APMIXED_IPPLL, 0x0374, 0x0380, 0x00000001,
+ 0, 22, 0x0378, 24, 0x0378, 0, 0),
+ PLL(CLK_APMIXED_DSPPLL, 0x0390, 0x039C, 0x00000001,
+ 0, 22, 0x0394, 24, 0x0394, 0, 0),
+ PLL(CLK_APMIXED_TCONPLL, 0x03A0, 0x03AC, 0x00000001,
+ 0, 22, 0x03A4, 24, 0x03A4, 0, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
+ FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+ FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
+ FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
+ FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
+ FACTOR0(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32),
+ FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
+ FACTOR0(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6),
+ FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12),
+ FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24),
+ FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+ FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20),
+ FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
+ FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14),
+ FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL2, 1, 2),
+ FACTOR1(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2),
+ FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
+ FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8),
+ FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16),
+ FACTOR1(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3),
+ FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6),
+ FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12),
+ FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24),
+ FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
+ FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10),
+ FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20),
+ FACTOR0(CLK_TOP_TCONPLL_D2, CLK_APMIXED_TCONPLL, 1, 2),
+ FACTOR0(CLK_TOP_TCONPLL_D4, CLK_APMIXED_TCONPLL, 1, 4),
+ FACTOR0(CLK_TOP_TCONPLL_D8, CLK_APMIXED_TCONPLL, 1, 8),
+ FACTOR0(CLK_TOP_TCONPLL_D16, CLK_APMIXED_TCONPLL, 1, 16),
+ FACTOR0(CLK_TOP_TCONPLL_D32, CLK_APMIXED_TCONPLL, 1, 32),
+ FACTOR0(CLK_TOP_TCONPLL_D64, CLK_APMIXED_TCONPLL, 1, 64),
+ FACTOR1(CLK_TOP_USB20_192M, CLK_TOP_UNIVPLL, 2, 13),
+ FACTOR1(CLK_TOP_USB20_192M_D2, CLK_TOP_USB20_192M, 1, 2),
+ FACTOR1(CLK_TOP_USB20_192M_D4_T, CLK_TOP_USB20_192M, 1, 4),
+ FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
+ FACTOR0(CLK_TOP_APLL1_D2, CLK_APMIXED_APLL1, 1, 2),
+ FACTOR0(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3),
+ FACTOR0(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4),
+ FACTOR0(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8),
+ FACTOR0(CLK_TOP_APLL1_D16, CLK_APMIXED_APLL1, 1, 16),
+ FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
+ FACTOR0(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2),
+ FACTOR0(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3),
+ FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4),
+ FACTOR0(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8),
+ FACTOR0(CLK_TOP_APLL2_D16, CLK_APMIXED_APLL2, 1, 16),
+ FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
+ FACTOR2(CLK_TOP_SYS_26M_D2, CLK_XTAL, 1, 2),
+ FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1),
+ FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2),
+ FACTOR0(CLK_TOP_DSPPLL, CLK_APMIXED_DSPPLL, 1, 1),
+ FACTOR0(CLK_TOP_DSPPLL_D2, CLK_APMIXED_DSPPLL, 1, 2),
+ FACTOR0(CLK_TOP_DSPPLL_D4, CLK_APMIXED_DSPPLL, 1, 4),
+ FACTOR0(CLK_TOP_DSPPLL_D8, CLK_APMIXED_DSPPLL, 1, 8),
+ FACTOR0(CLK_TOP_IPPLL, CLK_APMIXED_IPPLL, 1, 1),
+ FACTOR0(CLK_TOP_IPPLL_D2, CLK_APMIXED_IPPLL, 1, 2),
+ FACTOR1(CLK_TOP_NFI2X_CK_D2, CLK_TOP_NFI2X_SEL, 1, 2),
+};
+
+static const int axi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_UNIVPLL3_D2,
+ CLK_TOP_SYSPLL1_D8,
+ CLK_TOP_SYS_26M_D2,
+ CLK_TOP_CLK32K
+};
+
+static const int mem_parents[] = {
+ CLK_TOP_DSPPLL,
+ CLK_TOP_IPPLL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D3
+};
+
+static const int uart_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D8
+};
+
+static const int spi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_UNIVPLL3_D2,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_SYSPLL4_D2
+};
+
+static const int spis_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_SYSPLL4_D2
+};
+
+static const int msdc50_0_hc_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_SYSPLL2_D2
+};
+
+static const int msdc50_0_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MSDCPLL_D2,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_SYSPLL2_D4,
+ CLK_TOP_UNIVPLL2_D8
+};
+
+static const int msdc50_2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MSDCPLL,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_UNIVPLL1_D4
+};
+
+static const int audio_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D8,
+ CLK_TOP_APLL1_D4,
+ CLK_TOP_APLL2_D4
+};
+
+static const int aud_intbus_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_UNIVPLL3_D2,
+ CLK_TOP_APLL2_D8,
+ CLK_TOP_SYS_26M_D2,
+ CLK_TOP_APLL1_D8,
+ CLK_TOP_UNIVPLL3_D4
+};
+
+static const int hapll1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL1,
+ CLK_TOP_APLL1_D2,
+ CLK_TOP_APLL1_D3,
+ CLK_TOP_APLL1_D4,
+ CLK_TOP_APLL1_D8,
+ CLK_TOP_APLL1_D16,
+ CLK_TOP_SYS_26M_D2
+};
+
+static const int hapll2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL2,
+ CLK_TOP_APLL2_D2,
+ CLK_TOP_APLL2_D3,
+ CLK_TOP_APLL2_D4,
+ CLK_TOP_APLL2_D8,
+ CLK_TOP_APLL2_D16,
+ CLK_TOP_SYS_26M_D2
+};
+
+static const int asm_l_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL_D5
+};
+
+static const int aud_spdif_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D2,
+ CLK_TOP_DSPPLL
+};
+
+static const int aud_1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL1
+};
+
+static const int aud_2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL2
+};
+
+static const int ssusb_sys_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_UNIVPLL3_D2
+};
+
+static const int spm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D8
+};
+
+static const int i2c_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYS_26M_D2,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_UNIVPLL3_D2,
+ CLK_TOP_SYSPLL1_D8,
+ CLK_TOP_SYSPLL2_D8,
+ CLK_TOP_CLK32K
+};
+
+static const int pwm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_SYSPLL1_D8,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_SYS_26M_D2,
+ CLK_TOP_CLK32K
+};
+
+static const int dsp_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_DSPPLL,
+ CLK_TOP_DSPPLL_D2,
+ CLK_TOP_DSPPLL_D4,
+ CLK_TOP_DSPPLL_D8,
+ CLK_TOP_APLL2_D4,
+ CLK_TOP_SYS_26M_D2,
+ CLK_TOP_CLK32K
+};
+
+static const int nfi2x_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_SYSPLL_D7,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_SYSPLL2_D4,
+ CLK_TOP_MSDCPLL_D2,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_UNIVPLL_D5
+};
+
+static const int spinfi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D8,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_SYSPLL1_D8,
+ CLK_TOP_SYSPLL4_D2,
+ CLK_TOP_SYSPLL2_D4,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_UNIVPLL3_D2
+};
+
+static const int ecc_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL_D5,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_UNIVPLL_D3
+};
+
+static const int gcpu_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL2_D2
+};
+
+static const int gcpu_cpm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_UNIVPLL1_D4
+};
+
+static const int mbist_diag_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYS_26M_D2
+};
+
+static const int ip0_nna_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_DSPPLL,
+ CLK_TOP_DSPPLL_D2,
+ CLK_TOP_DSPPLL_D4,
+ CLK_TOP_IPPLL,
+ CLK_TOP_SYS_26M_D2,
+ CLK_TOP_IPPLL_D2,
+ CLK_TOP_MSDCPLL_D2
+};
+
+static const int ip2_wfst_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_IPPLL,
+ CLK_TOP_IPPLL_D2,
+ CLK_TOP_SYS_26M_D2,
+ CLK_TOP_MSDCPLL
+};
+
+static const int sflash_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D16,
+ CLK_TOP_SYSPLL2_D8,
+ CLK_TOP_SYSPLL3_D4,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_UNIVPLL1_D8,
+ CLK_TOP_USB20_192M_D2,
+ CLK_TOP_UNIVPLL2_D4
+};
+
+static const int sram_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_DSPPLL,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_APLL1,
+ CLK_TOP_APLL2,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_SYS_26M_D2
+};
+
+static const int mm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_SYSPLL_D5,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_UNIVPLL_D5,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_UNIVPLL_D3
+};
+
+static const int dpi0_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_TCONPLL_D2,
+ CLK_TOP_TCONPLL_D4,
+ CLK_TOP_TCONPLL_D8,
+ CLK_TOP_TCONPLL_D16,
+ CLK_TOP_TCONPLL_D32,
+ CLK_TOP_TCONPLL_D64
+};
+
+static const int dbg_atclk_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_UNIVPLL_D5
+};
+
+static const int occ_104m_parents[] = {
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_UNIVPLL2_D8
+};
+
+static const int occ_68m_parents[] = {
+ CLK_TOP_SYSPLL1_D8,
+ CLK_TOP_UNIVPLL2_D8
+};
+
+static const int occ_182m_parents[] = {
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_UNIVPLL2_D8
+};
+
+static const struct mtk_composite top_muxes[] = {
+ /* CLK_CFG_0 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, axi_parents,
+ 0x040, 0x044, 0x048, 0, 3, 7,
+ 0x4, 0, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, mem_parents,
+ 0x040, 0x044, 0x048, 8, 2, 15,
+ 0x4, 1, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_UART_SEL, uart_parents,
+ 0x040, 0x044, 0x048, 16, 1, 23,
+ 0x4, 2, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPI_SEL, spi_parents,
+ 0x040, 0x044, 0x048, 24, 3, 31,
+ 0x4, 3, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_1 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPIS_SEL, spis_parents,
+ 0x050, 0x054, 0x058, 0, 3, 7,
+ 0x4, 4, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents,
+ 0x050, 0x054, 0x058, 8, 2, 15,
+ 0x4, 5, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents,
+ 0x050, 0x054, 0x058, 16, 2, 23,
+ 0x4, 6, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents,
+ 0x050, 0x054, 0x058, 24, 3, 31,
+ 0x4, 7, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_2 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents,
+ 0x060, 0x064, 0x068, 0, 3, 7,
+ 0x4, 8, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, msdc50_0_parents,
+ 0x060, 0x064, 0x068, 8, 3, 15,
+ 0x4, 9, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUDIO_SEL, audio_parents,
+ 0x060, 0x064, 0x068, 16, 2, 23,
+ 0x4, 10, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents,
+ 0x060, 0x064, 0x068, 24, 3, 31,
+ 0x4, 11, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_3 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL1_SEL, hapll1_parents,
+ 0x070, 0x074, 0x078, 0, 3, 7,
+ 0x4, 12, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL2_SEL, hapll2_parents,
+ 0x070, 0x074, 0x078, 8, 3, 15,
+ 0x4, 13, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A2SYS_SEL, hapll1_parents,
+ 0x070, 0x074, 0x078, 16, 3, 23,
+ 0x4, 14, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A1SYS_SEL, hapll2_parents,
+ 0x070, 0x074, 0x078, 24, 3, 31,
+ 0x4, 15, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_4 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_L_SEL, asm_l_parents,
+ 0x080, 0x084, 0x088, 0, 2, 7,
+ 0x4, 16, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_M_SEL, asm_l_parents,
+ 0x080, 0x084, 0x088, 8, 2, 15,
+ 0x4, 17, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_H_SEL, asm_l_parents,
+ 0x080, 0x084, 0x088, 16, 2, 23,
+ 0x4, 18, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents,
+ 0x080, 0x084, 0x088, 24, 2, 31,
+ 0x4, 19, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_5 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_1_SEL, aud_1_parents,
+ 0x090, 0x094, 0x098, 0, 1, 7,
+ 0x4, 20, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_2_SEL, aud_2_parents,
+ 0x090, 0x094, 0x098, 8, 1, 15,
+ 0x4, 21, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents,
+ 0x090, 0x094, 0x098, 16, 2, 23,
+ 0x4, 22, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents,
+ 0x090, 0x094, 0x098, 24, 2, 31,
+ 0x4, 23, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_6 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, spm_parents,
+ 0x0a0, 0x0a4, 0x0a8, 0, 1, 7,
+ 0x4, 24, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_I2C_SEL, i2c_parents,
+ 0x0a0, 0x0a4, 0x0a8, 8, 3, 15,
+ 0x4, 25, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_PWM_SEL, pwm_parents,
+ 0x0a0, 0x0a4, 0x0a8, 16, 3, 23,
+ 0x4, 26, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DSP_SEL, dsp_parents,
+ 0x0a0, 0x0a4, 0x0a8, 24, 3, 31,
+ 0x4, 27, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_7 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_NFI2X_SEL, nfi2x_parents,
+ 0x0b0, 0x0b4, 0x0b8, 0, 3, 7,
+ 0x4, 28, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPINFI_SEL, spinfi_parents,
+ 0x0b0, 0x0b4, 0x0b8, 8, 3, 15,
+ 0x4, 29, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ECC_SEL, ecc_parents,
+ 0x0b0, 0x0b4, 0x0b8, 16, 2, 23,
+ 0x4, 30, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_SEL, gcpu_parents,
+ 0x0b0, 0x0b4, 0x0b8, 24, 3, 31,
+ 0x4, 31, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_8 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents,
+ 0x0c0, 0x0c4, 0x0c8, 0, 2, 7,
+ 0x8, 0, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MBIST_DIAG_SEL, mbist_diag_parents,
+ 0x0c0, 0x0c4, 0x0c8, 8, 1, 15,
+ 0x8, 1, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP0_NNA_SEL, ip0_nna_parents,
+ 0x0c0, 0x0c4, 0x0c8, 16, 3, 23,
+ 0x8, 2, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP1_NNA_SEL, ip0_nna_parents,
+ 0x0c0, 0x0c4, 0x0c8, 24, 3, 31,
+ 0x8, 3, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_9 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP2_WFST_SEL, ip2_wfst_parents,
+ 0x0d0, 0x0d4, 0x0d8, 0, 3, 7,
+ 0x8, 4, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SFLASH_SEL, sflash_parents,
+ 0x0d0, 0x0d4, 0x0d8, 8, 3, 15,
+ 0x8, 5, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SRAM_SEL, sram_parents,
+ 0x0d0, 0x0d4, 0x0d8, 16, 3, 23,
+ 0x8, 6, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MM_SEL, mm_parents,
+ 0x0d0, 0x0d4, 0x0d8, 24, 3, 31,
+ 0x8, 7, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_10 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DPI0_SEL, dpi0_parents,
+ 0x0e0, 0x0e4, 0x0e8, 0, 3, 7,
+ 0x8, 8, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents,
+ 0x0e0, 0x0e4, 0x0e8, 8, 2, 15,
+ 0x8, 9, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_104M_SEL, occ_104m_parents,
+ 0x0e0, 0x0e4, 0x0e8, 16, 1, 23,
+ 0x8, 10, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_68M_SEL, occ_68m_parents,
+ 0x0e0, 0x0e4, 0x0e8, 24, 1, 31,
+ 0x8, 11, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_11 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_182M_SEL, occ_182m_parents,
+ 0x0ec, 0x0f0, 0x0f4, 0, 2, 7,
+ 0x8, 12, CLK_MUX_SETCLR_UPD),
+};
+
+static const struct mtk_gate_regs top0_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x0,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x104,
+ .sta_ofs = 0x104,
+};
+
+#define GATE_TOP0(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP1(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate top_clks[] = {
+ /* TOP0 */
+ GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10),
+ GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11),
+ GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16),
+ GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17),
+ /* TOP1 */
+ GATE_TOP1(CLK_TOP_USB20_48M_EN, CLK_TOP_USB20_192M_D4_T, 8),
+ GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, CLK_TOP_USB20_192M_D4_T, 9),
+ GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22),
+ GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23),
+};
+
+static const struct mtk_gate_regs infra0_cg_regs = {
+ .set_ofs = 0x294,
+ .clr_ofs = 0x294,
+ .sta_ofs = 0x294,
+};
+
+static const struct mtk_gate_regs infra1_cg_regs = {
+ .set_ofs = 0x80,
+ .clr_ofs = 0x84,
+ .sta_ofs = 0x90,
+};
+
+static const struct mtk_gate_regs infra2_cg_regs = {
+ .set_ofs = 0x88,
+ .clr_ofs = 0x8c,
+ .sta_ofs = 0x94,
+};
+
+static const struct mtk_gate_regs infra3_cg_regs = {
+ .set_ofs = 0xa4,
+ .clr_ofs = 0xa8,
+ .sta_ofs = 0xac,
+};
+
+static const struct mtk_gate_regs infra4_cg_regs = {
+ .set_ofs = 0xc0,
+ .clr_ofs = 0xc4,
+ .sta_ofs = 0xc8,
+};
+
+static const struct mtk_gate_regs infra5_cg_regs = {
+ .set_ofs = 0xd0,
+ .clr_ofs = 0xd4,
+ .sta_ofs = 0xd8,
+};
+
+#define GATE_INFRA0(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_INFRA1(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_INFRA2(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra2_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_INFRA3(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra3_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_INFRA4(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra4_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_INFRA5(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra5_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate infra_clks[] = {
+ /* INFRA0 */
+ GATE_INFRA0(CLK_INFRA_DSP_AXI, CLK_TOP_AXI_SEL, 8),
+ /* INFRA1 */
+ GATE_INFRA1(CLK_INFRA_APXGPT, CLK_TOP_AXI_SEL, 6),
+ GATE_INFRA1(CLK_INFRA_ICUSB, CLK_TOP_AXI_SEL, 8),
+ GATE_INFRA1(CLK_INFRA_GCE, CLK_TOP_AXI_SEL, 9),
+ GATE_INFRA1(CLK_INFRA_THERM, CLK_TOP_AXI_SEL, 10),
+ GATE_INFRA1(CLK_INFRA_PWM_HCLK, CLK_TOP_AXI_SEL, 15),
+ GATE_INFRA1(CLK_INFRA_PWM1, CLK_TOP_PWM_SEL, 16),
+ GATE_INFRA1(CLK_INFRA_PWM2, CLK_TOP_PWM_SEL, 17),
+ GATE_INFRA1(CLK_INFRA_PWM3, CLK_TOP_PWM_SEL, 18),
+ GATE_INFRA1(CLK_INFRA_PWM4, CLK_TOP_PWM_SEL, 19),
+ GATE_INFRA1(CLK_INFRA_PWM5, CLK_TOP_PWM_SEL, 20),
+ GATE_INFRA1(CLK_INFRA_PWM, CLK_TOP_PWM_SEL, 21),
+ GATE_INFRA1(CLK_INFRA_UART0, CLK_TOP_UART_SEL, 22),
+ GATE_INFRA1(CLK_INFRA_UART1, CLK_TOP_UART_SEL, 23),
+ GATE_INFRA1(CLK_INFRA_UART2, CLK_TOP_UART_SEL, 24),
+ GATE_INFRA1(CLK_INFRA_DSP_UART, CLK_TOP_UART_SEL, 26),
+ GATE_INFRA1(CLK_INFRA_GCE_26M, CLK_TOP_CLK26M, 27),
+ GATE_INFRA1(CLK_INFRA_CQDMA_FPC, CLK_TOP_AXI_SEL, 28),
+ GATE_INFRA1(CLK_INFRA_BTIF, CLK_TOP_AXI_SEL, 31),
+ /* INFRA2 */
+ GATE_INFRA2(CLK_INFRA_SPI, CLK_TOP_SPI_SEL, 1),
+ GATE_INFRA2(CLK_INFRA_MSDC0, CLK_TOP_MSDC50_0_HC_SEL, 2),
+ GATE_INFRA2(CLK_INFRA_MSDC1, CLK_TOP_AXI_SEL, 4),
+ GATE_INFRA2(CLK_INFRA_DVFSRC, CLK_TOP_CLK26M, 7),
+ GATE_INFRA2(CLK_INFRA_GCPU, CLK_TOP_AXI_SEL, 8),
+ GATE_INFRA2(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 9),
+ GATE_INFRA2(CLK_INFRA_AUXADC, CLK_TOP_CLK26M, 10),
+ GATE_INFRA2(CLK_INFRA_AUXADC_MD, CLK_TOP_CLK26M, 14),
+ GATE_INFRA2(CLK_INFRA_AP_DMA, CLK_TOP_AXI_SEL, 18),
+ GATE_INFRA2(CLK_INFRA_DEBUGSYS, CLK_TOP_AXI_SEL, 24),
+ GATE_INFRA2(CLK_INFRA_AUDIO, CLK_TOP_AXI_SEL, 25),
+ GATE_INFRA2(CLK_INFRA_FLASHIF, CLK_TOP_SFLASH_SEL, 29),
+ /* INFRA3 */
+ GATE_INFRA3(CLK_INFRA_PWM_FB6, CLK_TOP_PWM_SEL, 0),
+ GATE_INFRA3(CLK_INFRA_PWM_FB7, CLK_TOP_PWM_SEL, 1),
+ GATE_INFRA3(CLK_INFRA_AUD_ASRC, CLK_TOP_AXI_SEL, 3),
+ GATE_INFRA3(CLK_INFRA_AUD_26M, CLK_TOP_CLK26M, 4),
+ GATE_INFRA3(CLK_INFRA_SPIS, CLK_TOP_AXI_SEL, 6),
+ GATE_INFRA3(CLK_INFRA_CQ_DMA, CLK_TOP_AXI_SEL, 27),
+ /* INFRA4 */
+ GATE_INFRA4(CLK_INFRA_AP_MSDC0, CLK_TOP_MSDC50_0_SEL, 7),
+ GATE_INFRA4(CLK_INFRA_MD_MSDC0, CLK_TOP_MSDC50_0_SEL, 8),
+ GATE_INFRA4(CLK_INFRA_MSDC0_SRC, CLK_TOP_MSDC50_0_SEL, 9),
+ GATE_INFRA4(CLK_INFRA_MSDC1_SRC, CLK_TOP_MSDC30_1_SEL, 10),
+ GATE_INFRA4(CLK_INFRA_IRRX_26M, CLK_TOP_AXI_SEL, 22),
+ GATE_INFRA4(CLK_INFRA_IRRX_32K, CLK_TOP_CLK32K, 23),
+ GATE_INFRA4(CLK_INFRA_I2C0_AXI, CLK_TOP_I2C_SEL, 24),
+ GATE_INFRA4(CLK_INFRA_I2C1_AXI, CLK_TOP_I2C_SEL, 25),
+ GATE_INFRA4(CLK_INFRA_I2C2_AXI, CLK_TOP_I2C_SEL, 26),
+ /* INFRA5 */
+ GATE_INFRA5(CLK_INFRA_NFI, CLK_TOP_NFI2X_CK_D2, 1),
+ GATE_INFRA5(CLK_INFRA_NFIECC, CLK_TOP_NFI2X_CK_D2, 2),
+ GATE_INFRA5(CLK_INFRA_NFI_HCLK, CLK_TOP_AXI_SEL, 3),
+ GATE_INFRA5(CLK_INFRA_SUSB_133, CLK_TOP_AXI_SEL, 7),
+ GATE_INFRA5(CLK_INFRA_USB_SYS, CLK_TOP_SSUSB_SYS_SEL, 9),
+ GATE_INFRA5(CLK_INFRA_USB_XHCI, CLK_TOP_SSUSB_XHCI_SEL, 11),
+};
+
+static const struct mtk_clk_tree mt8512_clk_tree = {
+ .xtal_rate = 26 * MHZ,
+ .xtal2_rate = 26 * MHZ,
+ .fdivs_offs = CLK_TOP_SYSPLL1_D2,
+ .muxes_offs = CLK_TOP_AXI_SEL,
+ .plls = apmixed_plls,
+ .fclks = top_fixed_clks,
+ .fdivs = top_fixed_divs,
+ .muxes = top_muxes,
+};
+
+static int mt8512_apmixedsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8512_clk_tree);
+}
+
+static int mt8512_topckgen_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8512_clk_tree);
+}
+
+static int mt8512_topckgen_cg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, top_clks);
+}
+
+static int mt8512_infracfg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, infra_clks);
+}
+
+static const struct udevice_id mt8512_apmixed_compat[] = {
+ { .compatible = "mediatek,mt8512-apmixedsys", },
+ { }
+};
+
+static const struct udevice_id mt8512_topckgen_compat[] = {
+ { .compatible = "mediatek,mt8512-topckgen", },
+ { }
+};
+
+static const struct udevice_id mt8512_topckgen_cg_compat[] = {
+ { .compatible = "mediatek,mt8512-topckgen-cg", },
+ { }
+};
+
+static const struct udevice_id mt8512_infracfg_compat[] = {
+ { .compatible = "mediatek,mt8512-infracfg", },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+ .name = "mt8512-apmixedsys",
+ .id = UCLASS_CLK,
+ .of_match = mt8512_apmixed_compat,
+ .probe = mt8512_apmixedsys_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_apmixedsys_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+ .name = "mt8512-topckgen",
+ .id = UCLASS_CLK,
+ .of_match = mt8512_topckgen_compat,
+ .probe = mt8512_topckgen_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_topckgen_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
+ .name = "mt8512-topckgen-cg",
+ .id = UCLASS_CLK,
+ .of_match = mt8512_topckgen_cg_compat,
+ .probe = mt8512_topckgen_cg_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_infracfg) = {
+ .name = "mt8512-infracfg",
+ .id = UCLASS_CLK,
+ .of_match = mt8512_infracfg_compat,
+ .probe = mt8512_infracfg_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/include/dt-bindings/clock/mt8512-clk.h b/include/dt-bindings/clock/mt8512-clk.h
new file mode 100644
index 0000000000..fdc3474c01
--- /dev/null
+++ b/include/dt-bindings/clock/mt8512-clk.h
@@ -0,0 +1,197 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8512_H
+#define _DT_BINDINGS_CLK_MT8512_H
+
+/* TOPCKGEN */
+
+#define CLK_TOP_CLK_NULL 0
+#define CLK_TOP_CLK32K 1
+#define CLK_TOP_SYSPLL1_D2 2
+#define CLK_TOP_SYSPLL1_D4 3
+#define CLK_TOP_SYSPLL1_D8 4
+#define CLK_TOP_SYSPLL1_D16 5
+#define CLK_TOP_SYSPLL_D3 6
+#define CLK_TOP_SYSPLL2_D2 7
+#define CLK_TOP_SYSPLL2_D4 8
+#define CLK_TOP_SYSPLL2_D8 9
+#define CLK_TOP_SYSPLL_D5 10
+#define CLK_TOP_SYSPLL3_D4 11
+#define CLK_TOP_SYSPLL_D7 12
+#define CLK_TOP_SYSPLL4_D2 13
+#define CLK_TOP_UNIVPLL 14
+#define CLK_TOP_UNIVPLL_D2 15
+#define CLK_TOP_UNIVPLL1_D2 16
+#define CLK_TOP_UNIVPLL1_D4 17
+#define CLK_TOP_UNIVPLL1_D8 18
+#define CLK_TOP_UNIVPLL_D3 19
+#define CLK_TOP_UNIVPLL2_D2 20
+#define CLK_TOP_UNIVPLL2_D4 21
+#define CLK_TOP_UNIVPLL2_D8 22
+#define CLK_TOP_UNIVPLL_D5 23
+#define CLK_TOP_UNIVPLL3_D2 24
+#define CLK_TOP_UNIVPLL3_D4 25
+#define CLK_TOP_TCONPLL_D2 26
+#define CLK_TOP_TCONPLL_D4 27
+#define CLK_TOP_TCONPLL_D8 28
+#define CLK_TOP_TCONPLL_D16 29
+#define CLK_TOP_TCONPLL_D32 30
+#define CLK_TOP_TCONPLL_D64 31
+#define CLK_TOP_USB20_192M 32
+#define CLK_TOP_USB20_192M_D2 33
+#define CLK_TOP_USB20_192M_D4_T 34
+#define CLK_TOP_APLL1 35
+#define CLK_TOP_APLL1_D2 36
+#define CLK_TOP_APLL1_D3 37
+#define CLK_TOP_APLL1_D4 38
+#define CLK_TOP_APLL1_D8 39
+#define CLK_TOP_APLL1_D16 40
+#define CLK_TOP_APLL2 41
+#define CLK_TOP_APLL2_D2 42
+#define CLK_TOP_APLL2_D3 43
+#define CLK_TOP_APLL2_D4 44
+#define CLK_TOP_APLL2_D8 45
+#define CLK_TOP_APLL2_D16 46
+#define CLK_TOP_CLK26M 47
+#define CLK_TOP_SYS_26M_D2 48
+#define CLK_TOP_MSDCPLL 49
+#define CLK_TOP_MSDCPLL_D2 50
+#define CLK_TOP_DSPPLL 51
+#define CLK_TOP_DSPPLL_D2 52
+#define CLK_TOP_DSPPLL_D4 53
+#define CLK_TOP_DSPPLL_D8 54
+#define CLK_TOP_IPPLL 55
+#define CLK_TOP_IPPLL_D2 56
+#define CLK_TOP_NFI2X_CK_D2 57
+#define CLK_TOP_AXI_SEL 58
+#define CLK_TOP_MEM_SEL 59
+#define CLK_TOP_UART_SEL 60
+#define CLK_TOP_SPI_SEL 61
+#define CLK_TOP_SPIS_SEL 62
+#define CLK_TOP_MSDC50_0_HC_SEL 63
+#define CLK_TOP_MSDC2_2_HC_SEL 64
+#define CLK_TOP_MSDC50_0_SEL 65
+#define CLK_TOP_MSDC50_2_SEL 66
+#define CLK_TOP_MSDC30_1_SEL 67
+#define CLK_TOP_AUDIO_SEL 68
+#define CLK_TOP_AUD_INTBUS_SEL 69
+#define CLK_TOP_HAPLL1_SEL 70
+#define CLK_TOP_HAPLL2_SEL 71
+#define CLK_TOP_A2SYS_SEL 72
+#define CLK_TOP_A1SYS_SEL 73
+#define CLK_TOP_ASM_L_SEL 74
+#define CLK_TOP_ASM_M_SEL 75
+#define CLK_TOP_ASM_H_SEL 76
+#define CLK_TOP_AUD_SPDIF_SEL 77
+#define CLK_TOP_AUD_1_SEL 78
+#define CLK_TOP_AUD_2_SEL 79
+#define CLK_TOP_SSUSB_SYS_SEL 80
+#define CLK_TOP_SSUSB_XHCI_SEL 81
+#define CLK_TOP_SPM_SEL 82
+#define CLK_TOP_I2C_SEL 83
+#define CLK_TOP_PWM_SEL 84
+#define CLK_TOP_DSP_SEL 85
+#define CLK_TOP_NFI2X_SEL 86
+#define CLK_TOP_SPINFI_SEL 87
+#define CLK_TOP_ECC_SEL 88
+#define CLK_TOP_GCPU_SEL 89
+#define CLK_TOP_GCPU_CPM_SEL 90
+#define CLK_TOP_MBIST_DIAG_SEL 91
+#define CLK_TOP_IP0_NNA_SEL 92
+#define CLK_TOP_IP1_NNA_SEL 93
+#define CLK_TOP_IP2_WFST_SEL 94
+#define CLK_TOP_SFLASH_SEL 95
+#define CLK_TOP_SRAM_SEL 96
+#define CLK_TOP_MM_SEL 97
+#define CLK_TOP_DPI0_SEL 98
+#define CLK_TOP_DBG_ATCLK_SEL 99
+#define CLK_TOP_OCC_104M_SEL 100
+#define CLK_TOP_OCC_68M_SEL 101
+#define CLK_TOP_OCC_182M_SEL 102
+
+/* TOPCKGEN Gates */
+#define CLK_TOP_CONN_32K 0
+#define CLK_TOP_CONN_26M 1
+#define CLK_TOP_DSP_32K 2
+#define CLK_TOP_DSP_26M 3
+#define CLK_TOP_USB20_48M_EN 4
+#define CLK_TOP_UNIVPLL_48M_EN 5
+#define CLK_TOP_SSUSB_TOP_CK_EN 6
+#define CLK_TOP_SSUSB_PHY_CK_EN 7
+#define CLK_TOP_I2SI1_MCK 8
+#define CLK_TOP_TDMIN_MCK 9
+#define CLK_TOP_I2SO1_MCK 10
+
+/* INFRASYS */
+
+#define CLK_INFRA_DSP_AXI 0
+#define CLK_INFRA_APXGPT 1
+#define CLK_INFRA_ICUSB 2
+#define CLK_INFRA_GCE 3
+#define CLK_INFRA_THERM 4
+#define CLK_INFRA_PWM_HCLK 5
+#define CLK_INFRA_PWM1 6
+#define CLK_INFRA_PWM2 7
+#define CLK_INFRA_PWM3 8
+#define CLK_INFRA_PWM4 9
+#define CLK_INFRA_PWM5 10
+#define CLK_INFRA_PWM 11
+#define CLK_INFRA_UART0 12
+#define CLK_INFRA_UART1 13
+#define CLK_INFRA_UART2 14
+#define CLK_INFRA_DSP_UART 15
+#define CLK_INFRA_GCE_26M 16
+#define CLK_INFRA_CQDMA_FPC 17
+#define CLK_INFRA_BTIF 18
+#define CLK_INFRA_SPI 19
+#define CLK_INFRA_MSDC0 20
+#define CLK_INFRA_MSDC1 21
+#define CLK_INFRA_DVFSRC 22
+#define CLK_INFRA_GCPU 23
+#define CLK_INFRA_TRNG 24
+#define CLK_INFRA_AUXADC 25
+#define CLK_INFRA_AUXADC_MD 26
+#define CLK_INFRA_AP_DMA 27
+#define CLK_INFRA_DEBUGSYS 28
+#define CLK_INFRA_AUDIO 29
+#define CLK_INFRA_FLASHIF 30
+#define CLK_INFRA_PWM_FB6 31
+#define CLK_INFRA_PWM_FB7 32
+#define CLK_INFRA_AUD_ASRC 33
+#define CLK_INFRA_AUD_26M 34
+#define CLK_INFRA_SPIS 35
+#define CLK_INFRA_CQ_DMA 36
+#define CLK_INFRA_AP_MSDC0 37
+#define CLK_INFRA_MD_MSDC0 38
+#define CLK_INFRA_MSDC0_SRC 39
+#define CLK_INFRA_MSDC1_SRC 40
+#define CLK_INFRA_IRRX_26M 41
+#define CLK_INFRA_IRRX_32K 42
+#define CLK_INFRA_I2C0_AXI 43
+#define CLK_INFRA_I2C1_AXI 44
+#define CLK_INFRA_I2C2_AXI 45
+#define CLK_INFRA_NFI 46
+#define CLK_INFRA_NFIECC 47
+#define CLK_INFRA_NFI_HCLK 48
+#define CLK_INFRA_SUSB_133 49
+#define CLK_INFRA_USB_SYS 50
+#define CLK_INFRA_USB_XHCI 51
+#define CLK_INFRA_NR_CLK 52
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL 0
+#define CLK_APMIXED_MAINPLL 1
+#define CLK_APMIXED_UNIVPLL2 2
+#define CLK_APMIXED_MSDCPLL 3
+#define CLK_APMIXED_APLL1 4
+#define CLK_APMIXED_APLL2 5
+#define CLK_APMIXED_IPPLL 6
+#define CLK_APMIXED_DSPPLL 7
+#define CLK_APMIXED_TCONPLL 8
+#define CLK_APMIXED_NR_CLK 9
+
+#endif /* _DT_BINDINGS_CLK_MT8512_H */
--
2.24.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 3/8] clk: mediatek: add set_clr_upd mux type flow
2019-12-31 3:29 [PATCH v2 0/8] Add support for MediaTek MT8512 Soc mingming lee
2019-12-31 3:29 ` [PATCH v2 1/8] ARM: MediaTek: Add support for MediaTek MT8512 SoC mingming lee
2019-12-31 3:29 ` [PATCH v2 2/8] clk: mediatek: add driver support for MT8512 mingming lee
@ 2019-12-31 3:29 ` mingming lee
2020-01-16 14:41 ` Tom Rini
2019-12-31 3:29 ` [PATCH v2 4/8] clk: mediatek: add configurable pcw_chg_reg/ibits/fmin to mtk_pll mingming lee
` (4 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: mingming lee @ 2019-12-31 3:29 UTC (permalink / raw)
To: u-boot
Add new set_clr_upd mux type and related operation to
mtk common clock driver to support mt8512
---
drivers/clk/mediatek/clk-mtk.c | 43 +++++++++++++++++++++++++---------
drivers/clk/mediatek/clk-mtk.h | 23 ++++++++++++++++++
2 files changed, 55 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 6c6b500d9b..450de981e9 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -67,12 +67,23 @@ static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent,
if (++index == mux->num_parents)
return -EINVAL;
- /* switch mux to a select parent */
- val = readl(base + mux->mux_reg);
- val &= ~(mux->mux_mask << mux->mux_shift);
+ if (mux->flags & CLK_MUX_SETCLR_UPD) {
+ val = (mux->mux_mask << mux->mux_shift);
+ writel(val, base + mux->mux_clr_reg);
- val |= index << mux->mux_shift;
- writel(val, base + mux->mux_reg);
+ val = (index << mux->mux_shift);
+ writel(val, base + mux->mux_set_reg);
+
+ if (mux->upd_shift >= 0)
+ writel(BIT(mux->upd_shift), base + mux->upd_reg);
+ } else {
+ /* switch mux to a select parent */
+ val = readl(base + mux->mux_reg);
+ val &= ~(mux->mux_mask << mux->mux_shift);
+
+ val |= index << mux->mux_shift;
+ writel(val, base + mux->mux_reg);
+ }
return 0;
}
@@ -332,9 +343,14 @@ static int mtk_topckgen_enable(struct clk *clk)
return 0;
/* enable clock gate */
- val = readl(priv->base + mux->gate_reg);
- val &= ~BIT(mux->gate_shift);
- writel(val, priv->base + mux->gate_reg);
+ if (mux->flags & CLK_MUX_SETCLR_UPD) {
+ val = BIT(mux->gate_shift);
+ writel(val, priv->base + mux->mux_clr_reg);
+ } else {
+ val = readl(priv->base + mux->gate_reg);
+ val &= ~BIT(mux->gate_shift);
+ writel(val, priv->base + mux->gate_reg);
+ }
if (mux->flags & CLK_DOMAIN_SCPSYS) {
/* enable scpsys clock off control */
@@ -360,9 +376,14 @@ static int mtk_topckgen_disable(struct clk *clk)
return 0;
/* disable clock gate */
- val = readl(priv->base + mux->gate_reg);
- val |= BIT(mux->gate_shift);
- writel(val, priv->base + mux->gate_reg);
+ if (mux->flags & CLK_MUX_SETCLR_UPD) {
+ val = BIT(mux->gate_shift);
+ writel(val, priv->base + mux->mux_set_reg);
+ } else {
+ val = readl(priv->base + mux->gate_reg);
+ val |= BIT(mux->gate_shift);
+ writel(val, priv->base + mux->gate_reg);
+ }
return 0;
}
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index dce93253ad..7ea0042500 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -12,6 +12,7 @@
#define HAVE_RST_BAR BIT(0)
#define CLK_DOMAIN_SCPSYS BIT(0)
+#define CLK_MUX_SETCLR_UPD BIT(1)
#define CLK_GATE_SETCLR BIT(0)
#define CLK_GATE_SETCLR_INV BIT(1)
@@ -102,9 +103,13 @@ struct mtk_composite {
const int id;
const int *parent;
u32 mux_reg;
+ u32 mux_set_reg;
+ u32 mux_clr_reg;
+ u32 upd_reg;
u32 gate_reg;
u32 mux_mask;
signed char mux_shift;
+ signed char upd_shift;
signed char gate_shift;
signed char num_parents;
u16 flags;
@@ -137,6 +142,24 @@ struct mtk_composite {
.flags = 0, \
}
+#define MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\
+ _mux_clr_ofs, _shift, _width, _gate, \
+ _upd_ofs, _upd, _flags) { \
+ .id = _id, \
+ .mux_reg = _mux_ofs, \
+ .mux_set_reg = _mux_set_ofs, \
+ .mux_clr_reg = _mux_clr_ofs, \
+ .upd_reg = _upd_ofs, \
+ .upd_shift = _upd, \
+ .mux_shift = _shift, \
+ .mux_mask = BIT(_width) - 1, \
+ .gate_reg = _mux_ofs, \
+ .gate_shift = _gate, \
+ .parent = _parents, \
+ .num_parents = ARRAY_SIZE(_parents), \
+ .flags = _flags, \
+ }
+
struct mtk_gate_regs {
u32 sta_ofs;
u32 clr_ofs;
--
2.24.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 4/8] clk: mediatek: add configurable pcw_chg_reg/ibits/fmin to mtk_pll
2019-12-31 3:29 [PATCH v2 0/8] Add support for MediaTek MT8512 Soc mingming lee
` (2 preceding siblings ...)
2019-12-31 3:29 ` [PATCH v2 3/8] clk: mediatek: add set_clr_upd mux type flow mingming lee
@ 2019-12-31 3:29 ` mingming lee
2020-01-16 14:41 ` Tom Rini
2020-01-16 14:41 ` Tom Rini
2019-12-31 3:29 ` [PATCH v2 5/8] pinctrl: mediatek: add driver for MT8512 mingming lee
` (3 subsequent siblings)
7 siblings, 2 replies; 18+ messages in thread
From: mingming lee @ 2019-12-31 3:29 UTC (permalink / raw)
To: u-boot
Add configurable pcw_chg_reg/ibits/fmin to mtk_pll to support mt8512
---
drivers/clk/mediatek/clk-mtk.c | 25 +++++++++++++++++--------
drivers/clk/mediatek/clk-mtk.h | 3 +++
2 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 450de981e9..334559161e 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -95,11 +95,13 @@ static unsigned long __mtk_pll_recalc_rate(const struct mtk_pll_data *pll,
{
int pcwbits = pll->pcwbits;
int pcwfbits;
+ int ibits;
u64 vco;
u8 c = 0;
/* The fractional part of the PLL divider. */
- pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
+ ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
+ pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0;
vco = (u64)fin * pcw;
@@ -124,7 +126,7 @@ static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw, int postdiv)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
- u32 val;
+ u32 val, chg;
/* set postdiv */
val = readl(priv->base + pll->pd_reg);
@@ -140,11 +142,16 @@ static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw, int postdiv)
/* set pcw */
val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift);
val |= pcw << pll->pcw_shift;
- val &= ~CON1_PCW_CHG;
- writel(val, priv->base + pll->pcw_reg);
- val |= CON1_PCW_CHG;
- writel(val, priv->base + pll->pcw_reg);
+ if (pll->pcw_chg_reg) {
+ chg = readl(priv->base + pll->pcw_chg_reg);
+ chg |= CON1_PCW_CHG;
+ writel(val, priv->base + pll->pcw_reg);
+ writel(chg, priv->base + pll->pcw_chg_reg);
+ } else {
+ val |= CON1_PCW_CHG;
+ writel(val, priv->base + pll->pcw_reg);
+ }
udelay(20);
}
@@ -161,8 +168,9 @@ static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv,
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
- unsigned long fmin = 1000 * MHZ;
+ unsigned long fmin = pll->fmin ? pll->fmin : 1000 * MHZ;
u64 _pcw;
+ int ibits;
u32 val;
if (freq > pll->fmax)
@@ -175,7 +183,8 @@ static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv,
}
/* _pcw = freq * postdiv / xtal_rate * 2^pcwfbits */
- _pcw = ((u64)freq << val) << (pll->pcwbits - INTEGER_BITS);
+ ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
+ _pcw = ((u64)freq << val) << (pll->pcwbits - ibits);
do_div(_pcw, priv->tree->xtal2_rate);
*pcw = (u32)_pcw;
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 7ea0042500..c7dc980861 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -37,9 +37,12 @@ struct mtk_pll_data {
u32 flags;
u32 rst_bar_mask;
u64 fmax;
+ u64 fmin;
int pcwbits;
+ int pcwibits;
u32 pcw_reg;
int pcw_shift;
+ u32 pcw_chg_reg;
};
/**
--
2.24.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 4/8] clk: mediatek: add configurable pcw_chg_reg/ibits/fmin to mtk_pll
2019-12-31 3:29 ` [PATCH v2 4/8] clk: mediatek: add configurable pcw_chg_reg/ibits/fmin to mtk_pll mingming lee
@ 2020-01-16 14:41 ` Tom Rini
2020-01-16 14:41 ` Tom Rini
1 sibling, 0 replies; 18+ messages in thread
From: Tom Rini @ 2020-01-16 14:41 UTC (permalink / raw)
To: u-boot
On Tue, Dec 31, 2019 at 11:29:22AM +0800, mingming lee wrote:
> Add configurable pcw_chg_reg/ibits/fmin to mtk_pll to support mt8512
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 4/8] clk: mediatek: add configurable pcw_chg_reg/ibits/fmin to mtk_pll
2019-12-31 3:29 ` [PATCH v2 4/8] clk: mediatek: add configurable pcw_chg_reg/ibits/fmin to mtk_pll mingming lee
2020-01-16 14:41 ` Tom Rini
@ 2020-01-16 14:41 ` Tom Rini
1 sibling, 0 replies; 18+ messages in thread
From: Tom Rini @ 2020-01-16 14:41 UTC (permalink / raw)
To: u-boot
On Tue, Dec 31, 2019 at 11:29:22AM +0800, mingming lee wrote:
> Add configurable pcw_chg_reg/ibits/fmin to mtk_pll to support mt8512
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 5/8] pinctrl: mediatek: add driver for MT8512
2019-12-31 3:29 [PATCH v2 0/8] Add support for MediaTek MT8512 Soc mingming lee
` (3 preceding siblings ...)
2019-12-31 3:29 ` [PATCH v2 4/8] clk: mediatek: add configurable pcw_chg_reg/ibits/fmin to mtk_pll mingming lee
@ 2019-12-31 3:29 ` mingming lee
2020-01-16 14:41 ` Tom Rini
2019-12-31 3:29 ` [PATCH v2 6/8] mmc: mtk-sd: add support for MediaTek MT8512/MT8110 SoCs mingming lee
` (2 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: mingming lee @ 2019-12-31 3:29 UTC (permalink / raw)
To: u-boot
Add Pinctrl driver for MediaTek MT8512 SoC.
Signed-off-by: mingming lee <mingming.lee@mediatek.com>
---
drivers/pinctrl/mediatek/Kconfig | 4 +
drivers/pinctrl/mediatek/Makefile | 1 +
drivers/pinctrl/mediatek/pinctrl-mt8512.c | 387 ++++++++++++++++++++++
3 files changed, 392 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8512.c
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 22ee62362b..9c6b580fde 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -12,6 +12,10 @@ config PINCTRL_MT7629
bool "MT7629 SoC pinctrl driver"
select PINCTRL_MTK
+config PINCTRL_MT8512
+ bool "MT8512 SoC pinctrl driver"
+ select PINCTRL_MTK
+
config PINCTRL_MT8516
bool "MT8516 SoC pinctrl driver"
select PINCTRL_MTK
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index 0ab7b1595b..ba955575cf 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -5,5 +5,6 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
+obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o
obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8512.c b/drivers/pinctrl/mediatek/pinctrl-mt8512.c
new file mode 100644
index 0000000000..af43754a4d
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8512.c
@@ -0,0 +1,387 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+#include <dm.h>
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, false)
+#define PIN_FIELDS(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, true)
+#define PIN_FIELD30(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 30, false)
+
+static const struct mtk_pin_field_calc mt8512_pin_mode_range[] = {
+ PIN_FIELD30(0, 115, 0x1E0, 0x10, 0, 3),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_dir_range[] = {
+ PIN_FIELD(0, 115, 0x140, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_di_range[] = {
+ PIN_FIELD(0, 115, 0x000, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_do_range[] = {
+ PIN_FIELD(0, 115, 0x860, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_pullen_range[] = {
+ PIN_FIELD(0, 115, 0x900, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_pullsel_range[] = {
+ PIN_FIELD(0, 115, 0x0A0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_ies_range[] = {
+ PIN_FIELDS(0, 2, 0x410, 0x10, 0, 1),
+ PIN_FIELDS(3, 5, 0x410, 0x10, 1, 1),
+ PIN_FIELDS(6, 7, 0x410, 0x10, 2, 1),
+ PIN_FIELDS(8, 11, 0x410, 0x10, 3, 1),
+ PIN_FIELDS(12, 15, 0x410, 0x10, 4, 1),
+ PIN_FIELDS(16, 19, 0x410, 0x10, 5, 1),
+ PIN_FIELD(20, 20, 0x410, 0x10, 6, 1),
+ PIN_FIELDS(21, 25, 0x410, 0x10, 7, 1),
+ PIN_FIELDS(26, 27, 0x410, 0x10, 8, 1),
+ PIN_FIELDS(28, 31, 0x410, 0x10, 9, 1),
+ PIN_FIELD(32, 32, 0x410, 0x10, 10, 1),
+ PIN_FIELDS(33, 39, 0x410, 0x10, 11, 1),
+ PIN_FIELD(40, 40, 0x410, 0x10, 12, 1),
+ PIN_FIELDS(41, 43, 0x410, 0x10, 13, 1),
+ PIN_FIELDS(44, 47, 0x410, 0x10, 14, 1),
+ PIN_FIELDS(48, 51, 0x410, 0x10, 15, 1),
+ PIN_FIELDS(52, 53, 0x410, 0x10, 16, 1),
+ PIN_FIELDS(54, 57, 0x410, 0x10, 17, 1),
+ PIN_FIELDS(58, 63, 0x410, 0x10, 18, 1),
+ PIN_FIELDS(64, 65, 0x410, 0x10, 19, 1),
+ PIN_FIELDS(66, 67, 0x410, 0x10, 20, 1),
+ PIN_FIELDS(68, 69, 0x410, 0x10, 21, 1),
+ PIN_FIELD(70, 70, 0x410, 0x10, 22, 1),
+ PIN_FIELD(71, 71, 0x410, 0x10, 23, 1),
+ PIN_FIELD(72, 72, 0x410, 0x10, 24, 1),
+ PIN_FIELD(73, 73, 0x410, 0x10, 25, 1),
+ PIN_FIELD(74, 74, 0x410, 0x10, 26, 1),
+ PIN_FIELD(75, 75, 0x410, 0x10, 27, 1),
+ PIN_FIELD(76, 76, 0x410, 0x10, 28, 1),
+ PIN_FIELD(77, 77, 0x410, 0x10, 29, 1),
+ PIN_FIELD(78, 78, 0x410, 0x10, 30, 1),
+ PIN_FIELD(79, 79, 0x410, 0x10, 31, 1),
+ PIN_FIELD(80, 80, 0x420, 0x10, 0, 1),
+ PIN_FIELD(81, 81, 0x420, 0x10, 1, 1),
+ PIN_FIELD(82, 82, 0x420, 0x10, 2, 1),
+ PIN_FIELD(83, 83, 0x420, 0x10, 3, 1),
+ PIN_FIELD(84, 84, 0x420, 0x10, 4, 1),
+ PIN_FIELDS(85, 86, 0x420, 0x10, 5, 1),
+ PIN_FIELD(87, 87, 0x420, 0x10, 6, 1),
+ PIN_FIELDS(88, 91, 0x420, 0x10, 7, 1),
+ PIN_FIELDS(92, 98, 0x420, 0x10, 8, 1),
+ PIN_FIELDS(99, 101, 0x420, 0x10, 9, 1),
+ PIN_FIELDS(102, 104, 0x420, 0x10, 10, 1),
+ PIN_FIELDS(105, 111, 0x420, 0x10, 11, 1),
+ PIN_FIELDS(112, 115, 0x420, 0x10, 12, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_smt_range[] = {
+ PIN_FIELDS(0, 2, 0x470, 0x10, 0, 1),
+ PIN_FIELDS(3, 5, 0x470, 0x10, 1, 1),
+ PIN_FIELDS(6, 7, 0x470, 0x10, 2, 1),
+ PIN_FIELDS(8, 11, 0x470, 0x10, 3, 1),
+ PIN_FIELDS(12, 15, 0x470, 0x10, 4, 1),
+ PIN_FIELDS(16, 19, 0x470, 0x10, 5, 1),
+ PIN_FIELD(20, 20, 0x470, 0x10, 6, 1),
+ PIN_FIELDS(21, 25, 0x470, 0x10, 7, 1),
+ PIN_FIELDS(26, 27, 0x470, 0x10, 8, 1),
+ PIN_FIELDS(28, 31, 0x470, 0x10, 9, 1),
+ PIN_FIELD(32, 32, 0x470, 0x10, 10, 1),
+ PIN_FIELDS(33, 39, 0x470, 0x10, 11, 1),
+ PIN_FIELD(40, 40, 0x470, 0x10, 12, 1),
+ PIN_FIELDS(41, 43, 0x470, 0x10, 13, 1),
+ PIN_FIELDS(44, 47, 0x470, 0x10, 14, 1),
+ PIN_FIELDS(48, 51, 0x470, 0x10, 15, 1),
+ PIN_FIELDS(52, 53, 0x470, 0x10, 16, 1),
+ PIN_FIELDS(54, 57, 0x470, 0x10, 17, 1),
+ PIN_FIELDS(58, 63, 0x470, 0x10, 18, 1),
+ PIN_FIELDS(64, 65, 0x470, 0x10, 19, 1),
+ PIN_FIELDS(66, 67, 0x470, 0x10, 20, 1),
+ PIN_FIELDS(68, 69, 0x470, 0x10, 21, 1),
+ PIN_FIELD(70, 70, 0x470, 0x10, 22, 1),
+ PIN_FIELD(71, 71, 0x470, 0x10, 23, 1),
+ PIN_FIELD(72, 72, 0x470, 0x10, 24, 1),
+ PIN_FIELD(73, 73, 0x470, 0x10, 25, 1),
+ PIN_FIELD(74, 74, 0x470, 0x10, 26, 1),
+ PIN_FIELD(75, 75, 0x470, 0x10, 27, 1),
+ PIN_FIELD(76, 76, 0x470, 0x10, 28, 1),
+ PIN_FIELD(77, 77, 0x470, 0x10, 29, 1),
+ PIN_FIELD(78, 78, 0x470, 0x10, 30, 1),
+ PIN_FIELD(79, 79, 0x470, 0x10, 31, 1),
+ PIN_FIELD(80, 80, 0x480, 0x10, 0, 1),
+ PIN_FIELD(81, 81, 0x480, 0x10, 1, 1),
+ PIN_FIELD(82, 82, 0x480, 0x10, 2, 1),
+ PIN_FIELD(83, 83, 0x480, 0x10, 3, 1),
+ PIN_FIELD(84, 84, 0x480, 0x10, 4, 1),
+ PIN_FIELDS(85, 86, 0x480, 0x10, 5, 1),
+ PIN_FIELD(87, 87, 0x480, 0x10, 6, 1),
+ PIN_FIELDS(88, 91, 0x480, 0x10, 7, 1),
+ PIN_FIELDS(92, 98, 0x480, 0x10, 8, 1),
+ PIN_FIELDS(99, 101, 0x480, 0x10, 9, 1),
+ PIN_FIELDS(102, 104, 0x480, 0x10, 10, 1),
+ PIN_FIELDS(105, 111, 0x480, 0x10, 11, 1),
+ PIN_FIELDS(112, 115, 0x480, 0x10, 12, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_drv_range[] = {
+ PIN_FIELDS(0, 2, 0x710, 0x10, 0, 4),
+ PIN_FIELDS(3, 5, 0x710, 0x10, 4, 4),
+ PIN_FIELDS(6, 7, 0x710, 0x10, 8, 4),
+ PIN_FIELDS(8, 11, 0x710, 0x10, 12, 4),
+ PIN_FIELDS(12, 15, 0x710, 0x10, 16, 4),
+ PIN_FIELDS(16, 19, 0x710, 0x10, 20, 4),
+ PIN_FIELD(20, 20, 0x710, 0x10, 24, 4),
+ PIN_FIELDS(21, 25, 0x710, 0x10, 28, 4),
+ PIN_FIELDS(26, 27, 0x720, 0x10, 0, 4),
+ PIN_FIELDS(28, 31, 0x720, 0x10, 4, 4),
+ PIN_FIELD(32, 32, 0x720, 0x10, 8, 4),
+ PIN_FIELDS(33, 39, 0x720, 0x10, 12, 4),
+ PIN_FIELD(40, 40, 0x720, 0x10, 16, 4),
+ PIN_FIELDS(41, 43, 0x720, 0x10, 20, 4),
+ PIN_FIELDS(44, 47, 0x720, 0x10, 24, 4),
+ PIN_FIELDS(48, 51, 0x720, 0x10, 28, 4),
+ PIN_FIELDS(52, 53, 0x730, 0x10, 0, 4),
+ PIN_FIELDS(54, 57, 0x730, 0x10, 4, 4),
+ PIN_FIELDS(58, 63, 0x730, 0x10, 8, 4),
+ PIN_FIELDS(64, 65, 0x730, 0x10, 12, 4),
+ PIN_FIELDS(66, 67, 0x730, 0x10, 16, 4),
+ PIN_FIELDS(68, 69, 0x730, 0x10, 20, 4),
+ PIN_FIELD(70, 70, 0x730, 0x10, 24, 4),
+ PIN_FIELD(71, 71, 0x730, 0x10, 28, 4),
+ PIN_FIELDS(72, 75, 0x740, 0x10, 0, 4),
+ PIN_FIELDS(76, 79, 0x740, 0x10, 16, 4),
+ PIN_FIELD(80, 80, 0x750, 0x10, 0, 4),
+ PIN_FIELD(81, 81, 0x750, 0x10, 4, 4),
+ PIN_FIELD(82, 82, 0x750, 0x10, 8, 4),
+ PIN_FIELDS(83, 86, 0x740, 0x10, 16, 4),
+ PIN_FIELD(87, 87, 0x750, 0x10, 24, 4),
+ PIN_FIELDS(88, 91, 0x750, 0x10, 28, 4),
+ PIN_FIELDS(92, 98, 0x760, 0x10, 0, 4),
+ PIN_FIELDS(99, 101, 0x760, 0x10, 4, 4),
+ PIN_FIELDS(102, 104, 0x760, 0x10, 8, 4),
+ PIN_FIELDS(105, 111, 0x760, 0x10, 12, 4),
+ PIN_FIELDS(112, 115, 0x760, 0x10, 16, 4),
+};
+
+static const struct mtk_pin_reg_calc mt8512_reg_cals[] = {
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8512_pin_mode_range),
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8512_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8512_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8512_pin_do_range),
+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8512_pin_ies_range),
+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8512_pin_smt_range),
+ [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8512_pin_pullsel_range),
+ [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8512_pin_pullen_range),
+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8512_pin_drv_range),
+};
+
+static const struct mtk_pin_desc mt8512_pins[] = {
+ MTK_PIN(0, "GPIO0", DRV_GRP4),
+ MTK_PIN(1, "GPIO1", DRV_GRP4),
+ MTK_PIN(2, "GPIO2", DRV_GRP4),
+ MTK_PIN(3, "GPIO3", DRV_GRP4),
+ MTK_PIN(4, "GPIO4", DRV_GRP4),
+ MTK_PIN(5, "GPIO5", DRV_GRP4),
+ MTK_PIN(6, "GPIO6", DRV_GRP4),
+ MTK_PIN(7, "GPIO7", DRV_GRP4),
+ MTK_PIN(8, "GPIO8", DRV_GRP4),
+ MTK_PIN(9, "GPIO9", DRV_GRP4),
+ MTK_PIN(10, "GPIO10", DRV_GRP4),
+ MTK_PIN(11, "GPIO11", DRV_GRP4),
+ MTK_PIN(12, "GPIO12", DRV_GRP4),
+ MTK_PIN(13, "GPIO13", DRV_GRP4),
+ MTK_PIN(14, "GPIO14", DRV_GRP4),
+ MTK_PIN(15, "GPIO15", DRV_GRP4),
+ MTK_PIN(16, "GPIO16", DRV_GRP4),
+ MTK_PIN(17, "GPIO17", DRV_GRP4),
+ MTK_PIN(18, "GPIO18", DRV_GRP4),
+ MTK_PIN(19, "GPIO19", DRV_GRP4),
+ MTK_PIN(20, "GPIO20", DRV_GRP4),
+ MTK_PIN(21, "AUDIO_SYNC", DRV_GRP4),
+ MTK_PIN(22, "WIFI_INTB", DRV_GRP4),
+ MTK_PIN(23, "BT_INTB", DRV_GRP4),
+ MTK_PIN(24, "BT_STEREO", DRV_GRP4),
+ MTK_PIN(25, "RSTNB", DRV_GRP4),
+ MTK_PIN(26, "USB_ID", DRV_GRP4),
+ MTK_PIN(27, "USB_DRV", DRV_GRP4),
+ MTK_PIN(28, "EINT_GAUGEING", DRV_GRP4),
+ MTK_PIN(29, "CHG_IRQ", DRV_GRP4),
+ MTK_PIN(30, "CHG_OTG", DRV_GRP4),
+ MTK_PIN(31, "CHG_CEB", DRV_GRP4),
+ MTK_PIN(32, "FL_EN", DRV_GRP4),
+ MTK_PIN(33, "WAN_SMS_RDY", DRV_GRP4),
+ MTK_PIN(34, "SOC2WAN_RESET", DRV_GRP4),
+ MTK_PIN(35, "WAN_FM_RDY", DRV_GRP4),
+ MTK_PIN(36, "WAN_DIS", DRV_GRP4),
+ MTK_PIN(37, "WAN_VBUS_EN", DRV_GRP4),
+ MTK_PIN(38, "WAN_VBAT_EN", DRV_GRP4),
+ MTK_PIN(39, "WAN_PWR_EN", DRV_GRP4),
+ MTK_PIN(40, "KPROW0", DRV_GRP4),
+ MTK_PIN(41, "KPROW1", DRV_GRP4),
+ MTK_PIN(42, "KPCOL0", DRV_GRP4),
+ MTK_PIN(43, "KPCOL1", DRV_GRP4),
+ MTK_PIN(44, "PWM0", DRV_GRP4),
+ MTK_PIN(45, "PWM1", DRV_GRP4),
+ MTK_PIN(46, "PWM2", DRV_GRP4),
+ MTK_PIN(47, "PWM3", DRV_GRP4),
+ MTK_PIN(48, "JTMS", DRV_GRP4),
+ MTK_PIN(49, "JTCK", DRV_GRP4),
+ MTK_PIN(50, "JTDI", DRV_GRP4),
+ MTK_PIN(51, "JTDO", DRV_GRP4),
+ MTK_PIN(52, "URXD0", DRV_GRP4),
+ MTK_PIN(53, "UTXD0", DRV_GRP4),
+ MTK_PIN(54, "URXD1", DRV_GRP4),
+ MTK_PIN(55, "UTXD1", DRV_GRP4),
+ MTK_PIN(56, "URTS1", DRV_GRP4),
+ MTK_PIN(57, "UCTS1", DRV_GRP4),
+ MTK_PIN(58, "RTC32K_CK", DRV_GRP4),
+ MTK_PIN(59, "PMIC_DVS_REQ0", DRV_GRP4),
+ MTK_PIN(60, "PMIC_DVS_REQ1", DRV_GRP4),
+ MTK_PIN(61, "WATCHDOG", DRV_GRP4),
+ MTK_PIN(62, "PMIC_INT", DRV_GRP4),
+ MTK_PIN(63, "SUSPEND", DRV_GRP4),
+ MTK_PIN(64, "SDA0", DRV_GRP4),
+ MTK_PIN(65, "SCL0", DRV_GRP4),
+ MTK_PIN(66, "SDA1", DRV_GRP4),
+ MTK_PIN(67, "SCL1", DRV_GRP4),
+ MTK_PIN(68, "SDA2", DRV_GRP4),
+ MTK_PIN(69, "SCL2", DRV_GRP4),
+ MTK_PIN(70, "MSDC1_CMD", DRV_GRP4),
+ MTK_PIN(71, "MSDC1_CLK", DRV_GRP4),
+ MTK_PIN(72, "MSDC1_DAT0", DRV_GRP4),
+ MTK_PIN(73, "MSDC1_DAT1", DRV_GRP4),
+ MTK_PIN(74, "MSDC1_DAT2", DRV_GRP4),
+ MTK_PIN(75, "MSDC1_DAT3", DRV_GRP4),
+ MTK_PIN(76, "MSDC0_DAT7", DRV_GRP4),
+ MTK_PIN(77, "MSDC0_DAT6", DRV_GRP4),
+ MTK_PIN(78, "MSDC0_DAT5", DRV_GRP4),
+ MTK_PIN(79, "MSDC0_DAT4", DRV_GRP4),
+ MTK_PIN(80, "MSDC0_RSTB", DRV_GRP4),
+ MTK_PIN(81, "MSDC0_CMD", DRV_GRP4),
+ MTK_PIN(82, "MSDC0_CLK", DRV_GRP4),
+ MTK_PIN(83, "MSDC0_DAT3", DRV_GRP4),
+ MTK_PIN(84, "MSDC0_DAT2", DRV_GRP4),
+ MTK_PIN(85, "MSDC0_DAT1", DRV_GRP4),
+ MTK_PIN(86, "MSDC0_DAT0", DRV_GRP4),
+ MTK_PIN(87, "SPDIF", DRV_GRP4),
+ MTK_PIN(88, "PCM_CLK", DRV_GRP4),
+ MTK_PIN(89, "PCM_SYNC", DRV_GRP4),
+ MTK_PIN(90, "PCM_RX", DRV_GRP4),
+ MTK_PIN(91, "PCM_TX", DRV_GRP4),
+ MTK_PIN(92, "I2SIN_MCLK", DRV_GRP4),
+ MTK_PIN(93, "I2SIN_LRCK", DRV_GRP4),
+ MTK_PIN(94, "I2SIN_BCK", DRV_GRP4),
+ MTK_PIN(95, "I2SIN_DAT0", DRV_GRP4),
+ MTK_PIN(96, "I2SIN_DAT1", DRV_GRP4),
+ MTK_PIN(97, "I2SIN_DAT2", DRV_GRP4),
+ MTK_PIN(98, "I2SIN_DAT3", DRV_GRP4),
+ MTK_PIN(99, "DMIC0_CLK", DRV_GRP4),
+ MTK_PIN(100, "DMIC0_DAT0", DRV_GRP4),
+ MTK_PIN(101, "DMIC0_DAT1", DRV_GRP4),
+ MTK_PIN(102, "DMIC1_CLK", DRV_GRP4),
+ MTK_PIN(103, "DMIC1_DAT0", DRV_GRP4),
+ MTK_PIN(104, "DMIC1_DAT1", DRV_GRP4),
+ MTK_PIN(105, "I2SO_BCK", DRV_GRP4),
+ MTK_PIN(106, "I2SO_LRCK", DRV_GRP4),
+ MTK_PIN(107, "I2SO_MCLK", DRV_GRP4),
+ MTK_PIN(108, "I2SO_DAT0", DRV_GRP4),
+ MTK_PIN(109, "I2SO_DAT1", DRV_GRP4),
+ MTK_PIN(110, "I2SO_DAT2", DRV_GRP4),
+ MTK_PIN(111, "I2SO_DAT3", DRV_GRP4),
+ MTK_PIN(112, "SPI_CSB", DRV_GRP4),
+ MTK_PIN(113, "SPI_CLK", DRV_GRP4),
+ MTK_PIN(114, "SPI_MISO", DRV_GRP4),
+ MTK_PIN(115, "SPI_MOSI", DRV_GRP4),
+};
+
+/* List all groups consisting of these pins dedicated to the enablement of
+ * certain hardware block and the corresponding mode for all of the pins.
+ * The hardware probably has multiple combinations of these pinouts.
+ */
+
+/* UART */
+static int mt8512_uart0_0_rxd_txd_pins[] = { 52, 53, };
+static int mt8512_uart0_0_rxd_txd_funcs[] = { 1, 1, };
+static int mt8512_uart1_0_rxd_txd_pins[] = { 54, 55, };
+static int mt8512_uart1_0_rxd_txd_funcs[] = { 1, 1, };
+static int mt8512_uart2_0_rxd_txd_pins[] = { 28, 29, };
+static int mt8512_uart2_0_rxd_txd_funcs[] = { 1, 1, };
+
+/* Joint those groups owning the same capability in user point of view which
+ * allows that people tend to use through the device tree.
+ */
+static const char *const mt8512_uart_groups[] = { "uart0_0_rxd_txd",
+ "uart1_0_rxd_txd",
+ "uart2_0_rxd_txd", };
+
+/* SNAND */
+static int mt8512_snfi_pins[] = { 71, 76, 77, 78, 79, 80, };
+static int mt8512_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
+
+/* MMC0 */
+static int mt8512_msdc0_pins[] = { 76, 77, 78, 79, 80, 81, 82, 83, 84,
+ 85, 86, };
+static int mt8512_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+
+static const struct mtk_group_desc mt8512_groups[] = {
+ PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8512_uart0_0_rxd_txd),
+ PINCTRL_PIN_GROUP("uart1_0_rxd_txd", mt8512_uart1_0_rxd_txd),
+ PINCTRL_PIN_GROUP("uart2_0_rxd_txd", mt8512_uart2_0_rxd_txd),
+
+ PINCTRL_PIN_GROUP("msdc0", mt8512_msdc0),
+
+ PINCTRL_PIN_GROUP("snfi", mt8512_snfi),
+};
+
+static const char *const mt8512_msdc_groups[] = { "msdc0" };
+
+static const struct mtk_function_desc mt8512_functions[] = {
+ {"uart", mt8512_uart_groups, ARRAY_SIZE(mt8512_uart_groups)},
+ {"msdc", mt8512_msdc_groups, ARRAY_SIZE(mt8512_msdc_groups)},
+ {"snand", mt8512_msdc_groups, ARRAY_SIZE(mt8512_msdc_groups)},
+};
+
+static struct mtk_pinctrl_soc mt8512_data = {
+ .name = "mt8512_pinctrl",
+ .reg_cal = mt8512_reg_cals,
+ .pins = mt8512_pins,
+ .npins = ARRAY_SIZE(mt8512_pins),
+ .grps = mt8512_groups,
+ .ngrps = ARRAY_SIZE(mt8512_groups),
+ .funcs = mt8512_functions,
+ .nfuncs = ARRAY_SIZE(mt8512_functions),
+};
+
+static int mtk_pinctrl_mt8512_probe(struct udevice *dev)
+{
+ return mtk_pinctrl_common_probe(dev, &mt8512_data);
+}
+
+static const struct udevice_id mt8512_pctrl_match[] = {
+ { .compatible = "mediatek,mt8512-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mt8512_pinctrl) = {
+ .name = "mt8512_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = mt8512_pctrl_match,
+ .ops = &mtk_pinctrl_ops,
+ .probe = mtk_pinctrl_mt8512_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
+};
--
2.24.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 6/8] mmc: mtk-sd: add support for MediaTek MT8512/MT8110 SoCs
2019-12-31 3:29 [PATCH v2 0/8] Add support for MediaTek MT8512 Soc mingming lee
` (4 preceding siblings ...)
2019-12-31 3:29 ` [PATCH v2 5/8] pinctrl: mediatek: add driver for MT8512 mingming lee
@ 2019-12-31 3:29 ` mingming lee
2020-01-16 14:41 ` Tom Rini
2019-12-31 3:29 ` [PATCH v2 7/8] mmc: mtk-sd: fix hang when data read quickly mingming lee
2019-12-31 3:29 ` [PATCH v2 8/8] ARM: MediaTek: add basic support for MT8512 boards mingming lee
7 siblings, 1 reply; 18+ messages in thread
From: mingming lee @ 2019-12-31 3:29 UTC (permalink / raw)
To: u-boot
This patch adds mmc support for MediaTek MT8512/MT8110 SoCs.
MT8512/MT8110 SoCs puts the tune register at top layer, so
need add new code to support it.
Signed-off-by: mingming lee <mingming.lee@mediatek.com>
---
drivers/mmc/mtk-sd.c | 134 ++++++++++++++++++++++++++++++++-----------
1 file changed, 101 insertions(+), 33 deletions(-)
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index eaa584a4df..23413731dc 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -12,6 +12,7 @@
#include <mmc.h>
#include <errno.h>
#include <malloc.h>
+#include <mapmem.h>
#include <stdbool.h>
#include <watchdog.h>
#include <asm/gpio.h>
@@ -135,6 +136,25 @@
#define SDC_FIFO_CFG_WRVALIDSEL BIT(24)
#define SDC_FIFO_CFG_RDVALIDSEL BIT(25)
+/* EMMC_TOP_CONTROL mask */
+#define PAD_RXDLY_SEL BIT(0)
+#define DELAY_EN BIT(1)
+#define PAD_DAT_RD_RXDLY2 (0x1f << 2)
+#define PAD_DAT_RD_RXDLY (0x1f << 7)
+#define PAD_DAT_RD_RXDLY_S 7
+#define PAD_DAT_RD_RXDLY2_SEL BIT(12)
+#define PAD_DAT_RD_RXDLY_SEL BIT(13)
+#define DATA_K_VALUE_SEL BIT(14)
+#define SDC_RX_ENH_EN BIT(15)
+
+/* EMMC_TOP_CMD mask */
+#define PAD_CMD_RXDLY2 (0x1f << 0)
+#define PAD_CMD_RXDLY (0x1f << 5)
+#define PAD_CMD_RXDLY_S 5
+#define PAD_CMD_RD_RXDLY2_SEL BIT(10)
+#define PAD_CMD_RD_RXDLY_SEL BIT(11)
+#define PAD_CMD_TX_DLY (0x1f << 12)
+
/* SDC_CFG_BUSWIDTH */
#define MSDC_BUS_1BITS 0x0
#define MSDC_BUS_4BITS 0x1
@@ -219,6 +239,21 @@ struct mtk_sd_regs {
u32 sdc_fifo_cfg;
};
+struct msdc_top_regs {
+ u32 emmc_top_control;
+ u32 emmc_top_cmd;
+ u32 emmc50_pad_ctl0;
+ u32 emmc50_pad_ds_tune;
+ u32 emmc50_pad_dat0_tune;
+ u32 emmc50_pad_dat1_tune;
+ u32 emmc50_pad_dat2_tune;
+ u32 emmc50_pad_dat3_tune;
+ u32 emmc50_pad_dat4_tune;
+ u32 emmc50_pad_dat5_tune;
+ u32 emmc50_pad_dat6_tune;
+ u32 emmc50_pad_dat7_tune;
+};
+
struct msdc_compatible {
u8 clk_div_bits;
u8 sclk_cycle_shift;
@@ -249,6 +284,7 @@ struct msdc_tune_para {
struct msdc_host {
struct mtk_sd_regs *base;
+ struct msdc_top_regs *top_base;
struct mmc *mmc;
struct msdc_compatible *dev_comp;
@@ -964,6 +1000,36 @@ static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
return delay_phase;
}
+static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
+{
+ void __iomem *tune_reg = &host->base->pad_tune;
+
+ if (host->dev_comp->pad_tune0)
+ tune_reg = &host->base->pad_tune0;
+
+ if (host->top_base)
+ clrsetbits_le32(&host->top_base->emmc_top_cmd, PAD_CMD_RXDLY,
+ value << PAD_CMD_RXDLY_S);
+ else
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
+ value << MSDC_PAD_TUNE_CMDRDLY_S);
+}
+
+static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
+{
+ void __iomem *tune_reg = &host->base->pad_tune;
+
+ if (host->dev_comp->pad_tune0)
+ tune_reg = &host->base->pad_tune0;
+
+ if (host->top_base)
+ clrsetbits_le32(&host->top_base->emmc_top_control,
+ PAD_DAT_RD_RXDLY, value << PAD_DAT_RD_RXDLY_S);
+ else
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
+ value << MSDC_PAD_TUNE_DATRRDLY_S);
+}
+
static int hs400_tune_response(struct udevice *dev, u32 opcode)
{
struct msdc_plat *plat = dev_get_platdata(dev);
@@ -1010,7 +1076,7 @@ static int hs400_tune_response(struct udevice *dev, u32 opcode)
PAD_CMD_TUNE_RX_DLY3_S);
final_delay = final_cmd_delay.final_phase;
- dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
+ dev_info(dev, "Final cmd pad delay: %x\n", final_delay);
return final_delay == 0xff ? -EIO : 0;
}
@@ -1217,21 +1283,14 @@ static int msdc_tune_together(struct udevice *dev, u32 opcode)
u32 rise_delay = 0, fall_delay = 0;
struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
u8 final_delay, final_maxlen;
- void __iomem *tune_reg = &host->base->pad_tune;
int i, ret;
- if (host->dev_comp->pad_tune0)
- tune_reg = &host->base->pad_tune0;
-
clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
for (i = 0; i < PAD_DELAY_MAX; i++) {
- clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
- i << MSDC_PAD_TUNE_CMDRDLY_S);
- clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
- i << MSDC_PAD_TUNE_DATRRDLY_S);
-
+ msdc_set_cmd_delay(host, i);
+ msdc_set_data_delay(host, i);
ret = mmc_send_tuning(mmc, opcode, NULL);
if (!ret)
rise_delay |= (1 << i);
@@ -1246,11 +1305,8 @@ static int msdc_tune_together(struct udevice *dev, u32 opcode)
setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
for (i = 0; i < PAD_DELAY_MAX; i++) {
- clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
- i << MSDC_PAD_TUNE_CMDRDLY_S);
- clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
- i << MSDC_PAD_TUNE_DATRRDLY_S);
-
+ msdc_set_cmd_delay(host, i);
+ msdc_set_data_delay(host, i);
ret = mmc_send_tuning(mmc, opcode, NULL);
if (!ret)
fall_delay |= (1 << i);
@@ -1263,27 +1319,17 @@ skip_fall:
if (final_maxlen == final_rise_delay.maxlen) {
clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
- clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
- final_rise_delay.final_phase <<
- MSDC_PAD_TUNE_CMDRDLY_S);
- clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
- final_rise_delay.final_phase <<
- MSDC_PAD_TUNE_DATRRDLY_S);
final_delay = final_rise_delay.final_phase;
} else {
setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
- clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
- final_fall_delay.final_phase <<
- MSDC_PAD_TUNE_CMDRDLY_S);
- clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
- final_fall_delay.final_phase <<
- MSDC_PAD_TUNE_DATRRDLY_S);
final_delay = final_fall_delay.final_phase;
}
- dev_err(dev, "Final pad delay: %x\n", final_delay);
+ msdc_set_cmd_delay(host, final_delay);
+ msdc_set_data_delay(host, final_delay);
+ dev_info(dev, "Final pad delay: %x\n", final_delay);
return final_delay == 0xff ? -EIO : 0;
}
@@ -1400,8 +1446,12 @@ static void msdc_init_hw(struct msdc_host *host)
3 << MSDC_PB2_RESPWAIT_S);
if (host->dev_comp->enhance_rx) {
- setbits_le32(&host->base->sdc_adv_cfg0,
- SDC_RX_ENHANCE_EN);
+ if (host->top_base)
+ setbits_le32(&host->top_base->emmc_top_control,
+ SDC_RX_ENH_EN);
+ else
+ setbits_le32(&host->base->sdc_adv_cfg0,
+ SDC_RX_ENHANCE_EN);
} else {
clrsetbits_le32(&host->base->patch_bit2,
MSDC_PB2_RESPSTSENSEL_M,
@@ -1476,7 +1526,6 @@ static int msdc_drv_probe(struct udevice *dev)
cfg->f_min = host->src_clk_freq / (4 * 255);
else
cfg->f_min = host->src_clk_freq / (4 * 4095);
- cfg->f_max = host->src_clk_freq / 2;
cfg->b_max = 1024;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
@@ -1502,11 +1551,19 @@ static int msdc_ofdata_to_platdata(struct udevice *dev)
struct msdc_plat *plat = dev_get_platdata(dev);
struct msdc_host *host = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
+ fdt_addr_t base, top_base;
int ret;
- host->base = (void *)dev_read_addr(dev);
- if (!host->base)
+ base = dev_read_addr(dev);
+ if (base == FDT_ADDR_T_NONE)
return -EINVAL;
+ host->base = map_sysmem(base, 0);
+
+ top_base = dev_read_addr_index(dev, 1);
+ if (top_base == FDT_ADDR_T_NONE)
+ host->top_base = NULL;
+ else
+ host->top_base = map_sysmem(top_base, 0);
ret = mmc_of_parse(dev, cfg);
if (ret)
@@ -1579,6 +1636,16 @@ static const struct msdc_compatible mt7623_compat = {
.enhance_rx = false
};
+static const struct msdc_compatible mt8512_compat = {
+ .clk_div_bits = 12,
+ .sclk_cycle_shift = 20,
+ .pad_tune0 = true,
+ .async_fifo = true,
+ .data_tune = true,
+ .busy_check = true,
+ .stop_clk_fix = true,
+};
+
static const struct msdc_compatible mt8516_compat = {
.clk_div_bits = 12,
.sclk_cycle_shift = 20,
@@ -1602,6 +1669,7 @@ static const struct msdc_compatible mt8183_compat = {
static const struct udevice_id msdc_ids[] = {
{ .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat },
{ .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
+ { .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat },
{ .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
{ .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat },
{}
--
2.24.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 7/8] mmc: mtk-sd: fix hang when data read quickly
2019-12-31 3:29 [PATCH v2 0/8] Add support for MediaTek MT8512 Soc mingming lee
` (5 preceding siblings ...)
2019-12-31 3:29 ` [PATCH v2 6/8] mmc: mtk-sd: add support for MediaTek MT8512/MT8110 SoCs mingming lee
@ 2019-12-31 3:29 ` mingming lee
2020-01-16 14:41 ` Tom Rini
2019-12-31 3:29 ` [PATCH v2 8/8] ARM: MediaTek: add basic support for MT8512 boards mingming lee
7 siblings, 1 reply; 18+ messages in thread
From: mingming lee @ 2019-12-31 3:29 UTC (permalink / raw)
To: u-boot
For CMD21 tuning data, the 128/64 bytes data may coming in very
short time, before msdc_start_data(), the read data has already
come, in this case, clear MSDC_INT will cause the interrupt disappear
and lead to the thread hang.
the solution is just clear all interrupts before command was sent.
Signed-off-by: mingming lee <mingming.lee@mediatek.com>
---
drivers/mmc/mtk-sd.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index 23413731dc..b0365877d7 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -14,7 +14,6 @@
#include <malloc.h>
#include <mapmem.h>
#include <stdbool.h>
-#include <watchdog.h>
#include <asm/gpio.h>
#include <dm/pinctrl.h>
#include <linux/bitops.h>
@@ -531,6 +530,7 @@ static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd,
blocks = data->blocks;
writel(CMD_INTS_MASK, &host->base->msdc_int);
+ writel(DATA_INTS_MASK, &host->base->msdc_int);
writel(blocks, &host->base->sdc_blk_num);
writel(cmd->cmdarg, &host->base->sdc_arg);
writel(rawcmd, &host->base->sdc_cmd);
@@ -677,13 +677,9 @@ static int msdc_start_data(struct msdc_host *host, struct mmc_data *data)
u32 size;
int ret;
- WATCHDOG_RESET();
-
if (data->flags == MMC_DATA_WRITE)
host->last_data_write = 1;
- writel(DATA_INTS_MASK, &host->base->msdc_int);
-
size = data->blocks * data->blocksize;
if (data->flags == MMC_DATA_WRITE)
--
2.24.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 7/8] mmc: mtk-sd: fix hang when data read quickly
2019-12-31 3:29 ` [PATCH v2 7/8] mmc: mtk-sd: fix hang when data read quickly mingming lee
@ 2020-01-16 14:41 ` Tom Rini
0 siblings, 0 replies; 18+ messages in thread
From: Tom Rini @ 2020-01-16 14:41 UTC (permalink / raw)
To: u-boot
On Tue, Dec 31, 2019 at 11:29:25AM +0800, mingming lee wrote:
> For CMD21 tuning data, the 128/64 bytes data may coming in very
> short time, before msdc_start_data(), the read data has already
> come, in this case, clear MSDC_INT will cause the interrupt disappear
> and lead to the thread hang.
>
> the solution is just clear all interrupts before command was sent.
>
> Signed-off-by: mingming lee <mingming.lee@mediatek.com>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 8/8] ARM: MediaTek: add basic support for MT8512 boards
2019-12-31 3:29 [PATCH v2 0/8] Add support for MediaTek MT8512 Soc mingming lee
` (6 preceding siblings ...)
2019-12-31 3:29 ` [PATCH v2 7/8] mmc: mtk-sd: fix hang when data read quickly mingming lee
@ 2019-12-31 3:29 ` mingming lee
2020-01-16 14:41 ` Tom Rini
7 siblings, 1 reply; 18+ messages in thread
From: mingming lee @ 2019-12-31 3:29 UTC (permalink / raw)
To: u-boot
This adds a general board file based on MT8512 SoCs from MediaTek.
Apart from the generic parts (cpu) we add some low level init codes
and initialize the early clocks.
This commit is adding the basic boot support for the MT8512 eMMC board.
Signed-off-by: mingming lee <mingming.lee@mediatek.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/mt8512-bm1-emmc.dts | 106 ++++++++++++++++++++++++++++++
board/mediatek/mt8512/Kconfig | 14 ++++
board/mediatek/mt8512/MAINTAINERS | 6 ++
board/mediatek/mt8512/Makefile | 3 +
board/mediatek/mt8512/mt8512.c | 19 ++++++
configs/mt8512_bm1_emmc_defconfig | 44 +++++++++++++
include/configs/mt8512.h | 60 +++++++++++++++++
8 files changed, 253 insertions(+)
create mode 100644 arch/arm/dts/mt8512-bm1-emmc.dts
create mode 100644 board/mediatek/mt8512/Kconfig
create mode 100644 board/mediatek/mt8512/MAINTAINERS
create mode 100644 board/mediatek/mt8512/Makefile
create mode 100644 board/mediatek/mt8512/mt8512.c
create mode 100644 configs/mt8512_bm1_emmc_defconfig
create mode 100644 include/configs/mt8512.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3dc9c4d41c..57cae40d83 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -835,6 +835,7 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
+ mt8512-bm1-emmc.dtb \
mt8516-pumpkin.dtb \
mt8518-ap1-emmc.dtb
diff --git a/arch/arm/dts/mt8512-bm1-emmc.dts b/arch/arm/dts/mt8512-bm1-emmc.dts
new file mode 100644
index 0000000000..296ed93b9e
--- /dev/null
+++ b/arch/arm/dts/mt8512-bm1-emmc.dts
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ *
+ */
+
+/dts-v1/;
+
+#include <config.h>
+#include "mt8512.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ model = "MT8512 BM1 EMMC";
+
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer0;
+ };
+
+ memory at 40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x20000000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_default>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ cap-mmc-hw-reset;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ non-removable;
+ status = "okay";
+};
+
+&pinctrl {
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "msdc";
+ groups = "msdc0";
+ };
+
+ conf-cmd-data {
+ pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1",
+ "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4",
+ "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7";
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "MSDC0_CLK";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ conf-rst {
+ pins = "MSDC0_RSTB";
+ bias-pull-up;
+ };
+ };
+
+ uart0_pins: uart0 {
+ mux {
+ function = "uart";
+ groups = "uart0_0_rxd_txd";
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/board/mediatek/mt8512/Kconfig b/board/mediatek/mt8512/Kconfig
new file mode 100644
index 0000000000..87bd1fbe69
--- /dev/null
+++ b/board/mediatek/mt8512/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_MT8512
+
+config SYS_BOARD
+ default "mt8512"
+
+config SYS_CONFIG_NAME
+ default "mt8512"
+
+
+config MTK_BROM_HEADER_INFO
+ string
+ default "media=nor"
+
+endif
diff --git a/board/mediatek/mt8512/MAINTAINERS b/board/mediatek/mt8512/MAINTAINERS
new file mode 100644
index 0000000000..966b1a749d
--- /dev/null
+++ b/board/mediatek/mt8512/MAINTAINERS
@@ -0,0 +1,6 @@
+MT8512
+M: Mingming lee <mingming.lee@mediatek.com>
+S: Maintained
+F: board/mediatek/mt8512
+F: include/configs/mt8512.h
+F: configs/mt8512_bm1_emmc_defconfig
diff --git a/board/mediatek/mt8512/Makefile b/board/mediatek/mt8512/Makefile
new file mode 100644
index 0000000000..c1f596b39d
--- /dev/null
+++ b/board/mediatek/mt8512/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += mt8512.o
diff --git a/board/mediatek/mt8512/mt8512.c b/board/mediatek/mt8512/mt8512.c
new file mode 100644
index 0000000000..726111d7d3
--- /dev/null
+++ b/board/mediatek/mt8512/mt8512.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <wdt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = gd->ram_base + 0x100;
+
+ debug("gd->fdt_blob is %p\n", gd->fdt_blob);
+ return 0;
+}
diff --git a/configs/mt8512_bm1_emmc_defconfig b/configs/mt8512_bm1_emmc_defconfig
new file mode 100644
index 0000000000..ee3b8e1ed1
--- /dev/null
+++ b/configs/mt8512_bm1_emmc_defconfig
@@ -0,0 +1,44 @@
+CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_SYS_TEXT_BASE=0x44e00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_TARGET_MT8512=y
+CONFIG_SYS_PROMPT="MT8512> "
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_OF_LIBFDT=y
+# CONFIG_FDT_DEBUG is not set
+CONFIG_LZMA=y
+CONFIG_LZ4=y
+CONFIG_LZO=y
+CONFIG_GZIP=y
+CONFIG_BZIP2=y
+CONFIG_CMD_BOOTMENU=y
+CONFIG_MENU_SHOW=y
+CONFIG_DEFAULT_FDT_FILE="mt8512-bm1-emmc.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="mt8512-bm1-emmc"
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MT8512=y
+CONFIG_PINCONF=y
+CONFIG_DM_GPIO=y
+CONFIG_RAM=y
+CONFIG_BAUDRATE=921600
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM=y
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_WDT=y
+CONFIG_WDT_MTK=y
+CONFIG_CLK=y
+CONFIG_TIMER=y
+CONFIG_MTK_TIMER=y
+CONFIG_CMD_MMC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MTK=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+# CONFIG_ENV_IS_IN_MMC is not set
diff --git a/include/configs/mt8512.h b/include/configs/mt8512.h
new file mode 100644
index 0000000000..253a54332c
--- /dev/null
+++ b/include/configs/mt8512.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for MediaTek MT8512 SoC
+ *
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+#ifndef __MT8512_H
+#define __MT8512_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
+
+#define CONFIG_CPU_ARMV8
+
+#define COUNTER_FREQUENCY 13000000
+
+#define CONFIG_SYS_LOAD_ADDR 0x41000000
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+#define CONFIG_SYS_MALLOC_LEN SZ_32M
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+
+/* Uboot definition */
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + \
+ SZ_2M - \
+ GENERATED_GBL_DATA_SIZE)
+
+/* ENV Setting */
+#if defined(CONFIG_MMC_MTK)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OVERWRITE
+
+/* MMC offset in block unit,and block size is 0x200 */
+#define ENV_BOOT_READ_IMAGE \
+ "boot_rd_img=mmc dev 0" \
+ ";mmc read ${loadaddr} 0x27000 0x8000" \
+ ";iminfo ${loadaddr}\0"
+#endif
+
+/* Console configuration */
+#define ENV_DEVICE_SETTINGS \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+
+#define ENV_BOOT_CMD \
+ "mtk_boot=run boot_rd_img;bootm;\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0x6c000000\0" \
+ ENV_DEVICE_SETTINGS \
+ ENV_BOOT_READ_IMAGE \
+ ENV_BOOT_CMD \
+ "bootcmd=run mtk_boot;\0" \
+
+#endif
--
2.24.1
^ permalink raw reply related [flat|nested] 18+ messages in thread