[RESEND v2 01/10] ARM: MediaTek: Add support for MediaTek MT7622 SoC

Sam Shih
2020-01-10T08:30:26Z

Add support for MediaTek MT7622 SoC. This include the file
that will initialize the SoC after boot and its device tree.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
---
arch/arm/dts/mt7622-u-boot.dtsi | 29 ++++
arch/arm/dts/mt7622.dtsi | 185 +++++++++++++++++++++++++
arch/arm/mach-mediatek/Kconfig | 9 ++
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt7622/Makefile | 3 +
arch/arm/mach-mediatek/mt7622/init.c | 51 +++++++
6 files changed, 278 insertions(+)
create mode 100644 arch/arm/dts/mt7622-u-boot.dtsi
create mode 100644 arch/arm/dts/mt7622.dtsi
create mode 100644 arch/arm/mach-mediatek/mt7622/Makefile
create mode 100644 arch/arm/mach-mediatek/mt7622/init.c

diff --git a/arch/arm/dts/mt7622-u-boot.dtsi b/arch/arm/dts/mt7622-u-boot.dtsi
new file mode 100644
index 0000000000..b14b1d4344
--- /dev/null
+++ b/arch/arm/dts/mt7622-u-boot.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+&topckgen {
+ u-boot,dm-pre-reloc;
+};
+
+&pericfg {
+ u-boot,dm-pre-reloc;
+};
+
+&apmixedsys {
+ u-boot,dm-pre-reloc;
+};
+
+&timer0 {
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&snfi {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
new file mode 100644
index 0000000000..7dcca5c6af
--- /dev/null
+++ b/arch/arm/dts/mt7622.dtsi
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mt7622-clk.h>
+
+/ {
+ compatible = "mediatek,mt7622";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ clock-frequency = <1300000000>;
+ };
+
+ cpu1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ clock-frequency = <1300000000>;
+ };
+ };
+
+ snfi: snfi at 1100d000 {
+ compatible = "mediatek,mtk-snfi-spi";
+ reg = <0x1100d000 0x2000>;
+ clocks = <&pericfg CLK_PERI_NFI_PD>,
+ <&pericfg CLK_PERI_SNFI_PD>;
+ clock-names = "nfi_clk", "pad_clk";
+ assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
+ <&topckgen CLK_TOP_NFI_INFRA_SEL>;
+
+ assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
+ <&topckgen CLK_TOP_UNIVPLL2_D8>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ timer0: timer at 10004000 {
+ compatible = "mediatek,timer";
+ reg = <0x10004000 0x80>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&system_clk>;
+ clock-names = "system-clk";
+ };
+
+ system_clk: dummy13m {
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+ #clock-cells = <0>;
+ };
+
+ infracfg: infracfg at 10000000 {
+ compatible = "mediatek,mt7622-infracfg",
+ "syscon";
+ reg = <0x10000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pericfg: pericfg at 10002000 {
+ compatible = "mediatek,mt7622-pericfg", "syscon";
+ reg = <0x10002000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ scpsys: scpsys at 10006000 {
+ compatible = "mediatek,mt7622-scpsys",
+ "syscon";
+ #power-domain-cells = <1>;
+ reg = <0x10006000 0x1000>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
+ infracfg = <&infracfg>;
+ clocks = <&topckgen CLK_TOP_HIF_SEL>;
+ clock-names = "hif_sel";
+ };
+
+ sysirq: interrupt-controller at 10200620 {
+ compatible = "mediatek,sysirq";
+ reg = <0x10200620 0x20>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ };
+
+ apmixedsys: apmixedsys at 10209000 {
+ compatible = "mediatek,mt7622-apmixedsys";
+ reg = <0x10209000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ topckgen: topckgen at 10210000 {
+ compatible = "mediatek,mt7622-topckgen";
+ reg = <0x10210000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pinctrl: pinctrl at 10211000 {
+ compatible = "mediatek,mt7622-pinctrl";
+ reg = <0x10211000 0x1000>;
+ gpio: gpio-controller {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ watchdog: watchdog at 10212000 {
+ compatible = "mediatek,wdt";
+ reg = <0x10212000 0x800>;
+ };
+
+ gic: interrupt-controller at 10300000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0x10310000 0x1000>,
+ <0x10320000 0x1000>,
+ <0x10340000 0x2000>,
+ <0x10360000 0x2000>;
+ };
+
+ uart0: serial at 11002000 {
+ compatible = "mediatek,hsuart";
+ reg = <0x11002000 0x400>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&pericfg CLK_PERI_UART0_PD>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
+ };
+
+ mmc0: mmc at 11230000 {
+ compatible = "mediatek,mt7622-mmc";
+ reg = <0x11230000 0x1000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
+ <&topckgen CLK_TOP_MSDC50_0_SEL>;
+ clock-names = "source", "hclk";
+ status = "disabled";
+ };
+
+ mmc1: mmc at 11240000 {
+ compatible = "mediatek,mt7622-mmc";
+ reg = <0x11240000 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
+ <&topckgen CLK_TOP_AXI_SEL>;
+ clock-names = "source", "hclk";
+ status = "disabled";
+ };
+};
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index ad453a60c1..908ca48b47 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -9,6 +9,14 @@ config SYS_VENDOR
choice
prompt "MediaTek board select"

+config TARGET_MT7622
+ bool "MediaTek MT7622 SoC"
+ select ARM64
+ help
+ The MediaTek MT7622 is a ARM64-based SoC with a dual-core Cortex-A53.
+ including UART, SPI, USB3.0, SD and MMC cards, NAND, SNFI, PWM, PCIe,
+ Gigabit Ethernet, I2C, built-in Wi-Fi, and PCIe.
+
config TARGET_MT7623
bool "MediaTek MT7623 SoC"
select CPU_V7A
@@ -49,6 +57,7 @@ config TARGET_MT8518

endchoice

+source "board/mediatek/mt7622/Kconfig"
source "board/mediatek/mt7623/Kconfig"
source "board/mediatek/mt7629/Kconfig"
source "board/mediatek/mt8518/Kconfig"
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index b9b2355e03..7e1e4a986c 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -3,6 +3,7 @@
obj-y += cpu.o
obj-$(CONFIG_SPL_BUILD) += spl.o

+obj-$(CONFIG_TARGET_MT7622) += mt7622/
obj-$(CONFIG_TARGET_MT7623) += mt7623/
obj-$(CONFIG_TARGET_MT7629) += mt7629/
obj-$(CONFIG_TARGET_MT8516) += mt8516/
diff --git a/arch/arm/mach-mediatek/mt7622/Makefile b/arch/arm/mach-mediatek/mt7622/Makefile
new file mode 100644
index 0000000000..886ab7e4eb
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7622/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
diff --git a/arch/arm/mach-mediatek/mt7622/init.c b/arch/arm/mach-mediatek/mt7622/init.c
new file mode 100644
index 0000000000..1e527c0485
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7622/init.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/armv8/mmu.h>
+
+int print_cpuinfo(void)
+{
+ printf("CPU: MediaTek MT7622\n");
+ return 0;
+}
+
+int dram_init(void)
+{
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ return ret;
+ return fdtdec_setup_mem_size_base();
+
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
+
+static struct mm_region mt7622_mem_map[] = {
+ {
+ /* DDR */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+ }, {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ 0,
+ }
+};
+struct mm_region *mem_map = mt7622_mem_map;
--
2.17.1