* [PATCH 1/3] clk: imx: imx8mn: add enet clk
@ 2020-02-14 16:08 Alifer Moraes
2020-02-14 16:08 ` [PATCH 2/3] clk: imx: imx8mn: add set_parent callback Alifer Moraes
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Alifer Moraes @ 2020-02-14 16:08 UTC (permalink / raw)
To: u-boot
Add enet ref/timer/PHY_REF/root clk wich are required to make enet work properly
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
---
drivers/clk/imx/clk-imx8mn.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index eb43971ae6..103ba770ed 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -80,6 +80,17 @@ static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_p
static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
"sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
+#ifndef CONFIG_SPL_BUILD
+static const char *imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
+ "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
+
+static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4", "video_pll1_out", };
+
+static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
+ "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
+#endif
+
static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
"sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
@@ -363,6 +374,14 @@ static int imx8mn_clk_probe(struct udevice *dev)
clk_dm(IMX8MN_CLK_USDHC3_ROOT,
imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
+/* clks not needed in SPL stage */
+#ifndef CONFIG_SPL_BUILD
+ clk_dm(IMX8MN_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels, base + 0xa980));
+ clk_dm(IMX8MN_CLK_ENET_TIMER, imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels, base + 0xaa00));
+ clk_dm(IMX8MN_CLK_ENET_PHY_REF, imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels, base + 0xaa80));
+ clk_dm(IMX8MN_CLK_ENET1_ROOT, imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0));
+#endif
+
#ifdef CONFIG_SPL_BUILD
struct clk *clkp, *clkp1;
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/3] clk: imx: imx8mn: add set_parent callback
2020-02-14 16:08 [PATCH 1/3] clk: imx: imx8mn: add enet clk Alifer Moraes
@ 2020-02-14 16:08 ` Alifer Moraes
2020-02-14 16:08 ` [PATCH 3/3] imx: imx8mn-evk: enable ethernet Alifer Moraes
2020-02-20 22:29 ` [PATCH 1/3] clk: imx: imx8mn: add enet clk Lukasz Majewski
2 siblings, 0 replies; 6+ messages in thread
From: Alifer Moraes @ 2020-02-14 16:08 UTC (permalink / raw)
To: u-boot
Add set_parent callback, then assigned-clock-parents in dts could work properly
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
---
drivers/clk/imx/clk-imx8mn.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 103ba770ed..2abd9a3810 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -175,11 +175,30 @@ static int imx8mn_clk_enable(struct clk *clk)
return __imx8mn_clk_enable(clk, 1);
}
+static int imx8mn_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *cp;
+ int ret;
+
+ debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_id(parent->id, &cp);
+ if (ret)
+ return ret;
+
+ return clk_set_parent(c, cp);
+}
+
static struct clk_ops imx8mn_clk_ops = {
.set_rate = imx8mn_clk_set_rate,
.get_rate = imx8mn_clk_get_rate,
.enable = imx8mn_clk_enable,
.disable = imx8mn_clk_disable,
+ .set_parent = imx8mn_clk_set_parent,
};
static int imx8mn_clk_probe(struct udevice *dev)
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/3] imx: imx8mn-evk: enable ethernet
2020-02-14 16:08 [PATCH 1/3] clk: imx: imx8mn: add enet clk Alifer Moraes
2020-02-14 16:08 ` [PATCH 2/3] clk: imx: imx8mn: add set_parent callback Alifer Moraes
@ 2020-02-14 16:08 ` Alifer Moraes
2020-02-20 22:29 ` [PATCH 1/3] clk: imx: imx8mn: add enet clk Lukasz Majewski
2 siblings, 0 replies; 6+ messages in thread
From: Alifer Moraes @ 2020-02-14 16:08 UTC (permalink / raw)
To: u-boot
Enable ethernet on i.MX 8MN EVK
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
---
arch/arm/dts/imx8mn-ddr4-evk.dts | 2 ++
board/freescale/imx8mn_evk/imx8mn_evk.c | 36 +++++++++++++++++++++++++
configs/imx8mn_ddr4_evk_defconfig | 8 ++++++
include/configs/imx8mn_evk.h | 2 ++
4 files changed, 48 insertions(+)
diff --git a/arch/arm/dts/imx8mn-ddr4-evk.dts b/arch/arm/dts/imx8mn-ddr4-evk.dts
index 9b2c1727a8..53ce10b13d 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk.dts
+++ b/arch/arm/dts/imx8mn-ddr4-evk.dts
@@ -165,6 +165,8 @@
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <ðphy0>;
+ phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <10>;
fsl,magic-packet;
status = "okay";
diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.c b/board/freescale/imx8mn_evk/imx8mn_evk.c
index 4f33c0e7c9..9ff1dc8555 100644
--- a/board/freescale/imx8mn_evk/imx8mn_evk.c
+++ b/board/freescale/imx8mn_evk/imx8mn_evk.c
@@ -4,6 +4,10 @@
*/
#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -14,8 +18,40 @@ int dram_init(void)
return 0;
}
+#if IS_ENABLED(CONFIG_FEC_MXC)
+static int setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* Use 125M anatop REF_CLK1 for ENET1, not from external */
+ clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /* enable rgmii rxc skew and phy mode select to RGMII copper */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ return 0;
+}
+#endif
+
int board_init(void)
{
+ if (IS_ENABLED(CONFIG_FEC_MXC))
+ setup_fec();
+
return 0;
}
diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig
index e3f99896a6..0e21283d58 100644
--- a/configs/imx8mn_ddr4_evk_defconfig
+++ b/configs/imx8mn_ddr4_evk_defconfig
@@ -43,6 +43,9 @@ CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
@@ -67,7 +70,12 @@ CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h
index ce73ca6b0a..bfc1a55637 100644
--- a/include/configs/imx8mn_evk.h
+++ b/include/configs/imx8mn_evk.h
@@ -149,4 +149,6 @@
#define CONFIG_SYS_I2C_SPEED 100000
+#define FEC_QUIRK_ENET_MAC
+
#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 1/3] clk: imx: imx8mn: add enet clk
2020-02-14 16:08 [PATCH 1/3] clk: imx: imx8mn: add enet clk Alifer Moraes
2020-02-14 16:08 ` [PATCH 2/3] clk: imx: imx8mn: add set_parent callback Alifer Moraes
2020-02-14 16:08 ` [PATCH 3/3] imx: imx8mn-evk: enable ethernet Alifer Moraes
@ 2020-02-20 22:29 ` Lukasz Majewski
2020-02-21 11:13 ` Alifer Moraes
2 siblings, 1 reply; 6+ messages in thread
From: Lukasz Majewski @ 2020-02-20 22:29 UTC (permalink / raw)
To: u-boot
Hi Alifer,
> Add enet ref/timer/PHY_REF/root clk wich are required to make enet
> work properly
Why have you sent those patches twice?
>
> Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
> ---
> drivers/clk/imx/clk-imx8mn.c | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-imx8mn.c
> b/drivers/clk/imx/clk-imx8mn.c index eb43971ae6..103ba770ed 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -80,6 +80,17 @@ static const char *imx8mn_ahb_sels[] =
> {"clock-osc-24m", "sys_pll1_133m", "sys_p static const char
> *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m",
> "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
> "video_pll1_out", "sys_pll3_out", }; +#ifndef CONFIG_SPL_BUILD
> +static const char *imx8mn_enet_ref_sels[] = {"clock-osc-24m",
> "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
> + "sys_pll1_160m",
> "audio_pll1_out", "video_pll1_out", "clk_ext4", }; +
> +static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m",
> "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
> + "clk_ext3",
> "clk_ext4", "video_pll1_out", }; +
> +static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m",
> "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
> + "sys_pll2_500m",
> "video_pll1_out", "audio_pll2_out", }; +#endif
> +
> static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m",
> "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll1_133m",
> "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
> @@ -363,6 +374,14 @@ static int imx8mn_clk_probe(struct udevice *dev)
> clk_dm(IMX8MN_CLK_USDHC3_ROOT,
> imx_clk_gate4("usdhc3_root_clk", "usdhc3", base +
> 0x45e0, 0));
> +/* clks not needed in SPL stage */
> +#ifndef CONFIG_SPL_BUILD
> + clk_dm(IMX8MN_CLK_ENET_REF, imx8m_clk_composite("enet_ref",
> imx8mn_enet_ref_sels, base + 0xa980));
> + clk_dm(IMX8MN_CLK_ENET_TIMER,
> imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels, base +
> 0xaa00));
> + clk_dm(IMX8MN_CLK_ENET_PHY_REF,
> imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels, base + 0xaa80));
> + clk_dm(IMX8MN_CLK_ENET1_ROOT,
> imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0));
> +#endif +
> #ifdef CONFIG_SPL_BUILD
> struct clk *clkp, *clkp1;
>
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 1/3] clk: imx: imx8mn: add enet clk
2020-02-20 22:29 ` [PATCH 1/3] clk: imx: imx8mn: add enet clk Lukasz Majewski
@ 2020-02-21 11:13 ` Alifer Moraes
2020-02-21 11:21 ` Lukasz Majewski
0 siblings, 1 reply; 6+ messages in thread
From: Alifer Moraes @ 2020-02-21 11:13 UTC (permalink / raw)
To: u-boot
Hello Lukasz,
> Why have you sent those patches twice?
>
I'm sorry for that, the first time I sent this patch I forgot to send
to u-boot lists too, so I sent it again.
Regards,
Alifer
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/3] clk: imx: imx8mn: add enet clk
2020-02-21 11:13 ` Alifer Moraes
@ 2020-02-21 11:21 ` Lukasz Majewski
0 siblings, 0 replies; 6+ messages in thread
From: Lukasz Majewski @ 2020-02-21 11:21 UTC (permalink / raw)
To: u-boot
Hi Alifer,
> Hello Lukasz,
>
> > Why have you sent those patches twice?
> >
>
> I'm sorry for that,
I was just curious if you made a v2 :-)
> the first time I sent this patch I forgot to send
> to u-boot lists too, so I sent it again.
>
> Regards,
> Alifer
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply [flat|nested] 6+ messages in thread
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Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2020-02-14 16:08 [PATCH 1/3] clk: imx: imx8mn: add enet clk Alifer Moraes
2020-02-14 16:08 ` [PATCH 2/3] clk: imx: imx8mn: add set_parent callback Alifer Moraes
2020-02-14 16:08 ` [PATCH 3/3] imx: imx8mn-evk: enable ethernet Alifer Moraes
2020-02-20 22:29 ` [PATCH 1/3] clk: imx: imx8mn: add enet clk Lukasz Majewski
2020-02-21 11:13 ` Alifer Moraes
2020-02-21 11:21 ` Lukasz Majewski
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