* [PATCH 1/2] mtd: spi-nor: Enable QE bit for ISSI flash
@ 2020-04-20 10:06 Jagan Teki
2020-04-20 10:06 ` [PATCH 2/2] mtd: spi-nor-ids: Enable 4B_OPCODES for is25wp256 Jagan Teki
2020-04-20 16:26 ` [PATCH 1/2] mtd: spi-nor: Enable QE bit for ISSI flash Sagar Kadam
0 siblings, 2 replies; 6+ messages in thread
From: Jagan Teki @ 2020-04-20 10:06 UTC (permalink / raw)
To: u-boot
Enable QE bit for ISSI flash chips.
QE enablement logic is similar to what Micromax
has, so reuse the existing code itself.
Cc: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/mtd/spi/spi-nor-core.c | 1 +
include/linux/mtd/spi-nor.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 7b6ad495ac..e0f6e4d6c3 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -325,6 +325,7 @@ static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
case SNOR_MFR_MICRON:
/* Some Micron need WREN command; all will accept it */
need_wren = true;
+ case SNOR_MFR_ISSI:
case SNOR_MFR_MACRONIX:
case SNOR_MFR_WINBOND:
if (need_wren)
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index ec144a08d8..233fdc341a 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -22,6 +22,7 @@
#define SNOR_MFR_INTEL CFI_MFR_INTEL
#define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */
#define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */
+#define SNOR_MFR_ISSI CFI_MFR_PMC
#define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
#define SNOR_MFR_SPANSION CFI_MFR_AMD
#define SNOR_MFR_SST CFI_MFR_SST
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] mtd: spi-nor-ids: Enable 4B_OPCODES for is25wp256
2020-04-20 10:06 [PATCH 1/2] mtd: spi-nor: Enable QE bit for ISSI flash Jagan Teki
@ 2020-04-20 10:06 ` Jagan Teki
2020-04-20 16:31 ` Sagar Kadam
2020-04-20 16:26 ` [PATCH 1/2] mtd: spi-nor: Enable QE bit for ISSI flash Sagar Kadam
1 sibling, 1 reply; 6+ messages in thread
From: Jagan Teki @ 2020-04-20 10:06 UTC (permalink / raw)
To: u-boot
IS25WP256 flash chips do support 4byte address opcodes,
so enable support for it.
Cc: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/mtd/spi/spi-nor-ids.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 973b6f86c9..f95bfb59e6 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -135,7 +135,8 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_4B_OPCODES) },
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
/* Macronix */
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 1/2] mtd: spi-nor: Enable QE bit for ISSI flash
2020-04-20 10:06 [PATCH 1/2] mtd: spi-nor: Enable QE bit for ISSI flash Jagan Teki
2020-04-20 10:06 ` [PATCH 2/2] mtd: spi-nor-ids: Enable 4B_OPCODES for is25wp256 Jagan Teki
@ 2020-04-20 16:26 ` Sagar Kadam
2020-04-20 16:27 ` Jagan Teki
1 sibling, 1 reply; 6+ messages in thread
From: Sagar Kadam @ 2020-04-20 16:26 UTC (permalink / raw)
To: u-boot
Hi Jagan,
> -----Original Message-----
> From: Jagan Teki <jagan@amarulasolutions.com>
> Sent: Monday, April 20, 2020 3:36 PM
> To: Vignesh R <vigneshr@ti.com>; u-boot at lists.denx.de
> Cc: Bin Meng <bmeng.cn@gmail.com>; linux-
> amarula at amarulasolutions.com; Jagan Teki
> <jagan@amarulasolutions.com>; Sagar Kadam <sagar.kadam@sifive.com>
> Subject: [PATCH 1/2] mtd: spi-nor: Enable QE bit for ISSI flash
>
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
>
> Enable QE bit for ISSI flash chips.
>
> QE enablement logic is similar to what Micromax has, so reuse the existing
> code itself.
nits: s/Micromax/Macronix
Thanks,
Sagar Kadam
>
> Cc: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> drivers/mtd/spi/spi-nor-core.c | 1 +
> include/linux/mtd/spi-nor.h | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> index 7b6ad495ac..e0f6e4d6c3 100644
> --- a/drivers/mtd/spi/spi-nor-core.c
> +++ b/drivers/mtd/spi/spi-nor-core.c
> @@ -325,6 +325,7 @@ static int set_4byte(struct spi_nor *nor, const struct
> flash_info *info,
> case SNOR_MFR_MICRON:
> /* Some Micron need WREN command; all will accept it */
> need_wren = true;
> + case SNOR_MFR_ISSI:
> case SNOR_MFR_MACRONIX:
> case SNOR_MFR_WINBOND:
> if (need_wren)
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index
> ec144a08d8..233fdc341a 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -22,6 +22,7 @@
> #define SNOR_MFR_INTEL CFI_MFR_INTEL
> #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */
> #define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <-->
> Micron */
> +#define SNOR_MFR_ISSI CFI_MFR_PMC
> #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
> #define SNOR_MFR_SPANSION CFI_MFR_AMD
> #define SNOR_MFR_SST CFI_MFR_SST
> --
> 2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] mtd: spi-nor: Enable QE bit for ISSI flash
2020-04-20 16:26 ` [PATCH 1/2] mtd: spi-nor: Enable QE bit for ISSI flash Sagar Kadam
@ 2020-04-20 16:27 ` Jagan Teki
2020-04-20 19:17 ` Sagar Kadam
0 siblings, 1 reply; 6+ messages in thread
From: Jagan Teki @ 2020-04-20 16:27 UTC (permalink / raw)
To: u-boot
On Mon, Apr 20, 2020 at 9:56 PM Sagar Kadam <sagar.kadam@sifive.com> wrote:
>
> Hi Jagan,
>
> > -----Original Message-----
> > From: Jagan Teki <jagan@amarulasolutions.com>
> > Sent: Monday, April 20, 2020 3:36 PM
> > To: Vignesh R <vigneshr@ti.com>; u-boot at lists.denx.de
> > Cc: Bin Meng <bmeng.cn@gmail.com>; linux-
> > amarula at amarulasolutions.com; Jagan Teki
> > <jagan@amarulasolutions.com>; Sagar Kadam <sagar.kadam@sifive.com>
> > Subject: [PATCH 1/2] mtd: spi-nor: Enable QE bit for ISSI flash
> >
> > [External Email] Do not click links or attachments unless you recognize the
> > sender and know the content is safe
> >
> > Enable QE bit for ISSI flash chips.
> >
> > QE enablement logic is similar to what Micromax has, so reuse the existing
> > code itself.
>
> nits: s/Micromax/Macronix
Will update while applying, thanks.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] mtd: spi-nor-ids: Enable 4B_OPCODES for is25wp256
2020-04-20 10:06 ` [PATCH 2/2] mtd: spi-nor-ids: Enable 4B_OPCODES for is25wp256 Jagan Teki
@ 2020-04-20 16:31 ` Sagar Kadam
0 siblings, 0 replies; 6+ messages in thread
From: Sagar Kadam @ 2020-04-20 16:31 UTC (permalink / raw)
To: u-boot
Hi Jagan,
> -----Original Message-----
> From: Jagan Teki <jagan@amarulasolutions.com>
> Sent: Monday, April 20, 2020 3:36 PM
> To: Vignesh R <vigneshr@ti.com>; u-boot at lists.denx.de
> Cc: Bin Meng <bmeng.cn@gmail.com>; linux-
> amarula at amarulasolutions.com; Jagan Teki
> <jagan@amarulasolutions.com>; Sagar Kadam <sagar.kadam@sifive.com>
> Subject: [PATCH 2/2] mtd: spi-nor-ids: Enable 4B_OPCODES for is25wp256
>
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
>
> IS25WP256 flash chips do support 4byte address opcodes,
> so enable support for it.
>
> Cc: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> drivers/mtd/spi/spi-nor-ids.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index 973b6f86c9..f95bfb59e6 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -135,7 +135,8 @@ const struct flash_info spi_nor_ids[] = {
> { INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256,
> SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512,
> - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> + SPI_NOR_4B_OPCODES) },
Looks good thanks for including.
Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com>
Thanks & BR,
Sagar Kadam
> #endif
> #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
> /* Macronix */
> --
> 2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] mtd: spi-nor: Enable QE bit for ISSI flash
2020-04-20 16:27 ` Jagan Teki
@ 2020-04-20 19:17 ` Sagar Kadam
0 siblings, 0 replies; 6+ messages in thread
From: Sagar Kadam @ 2020-04-20 19:17 UTC (permalink / raw)
To: u-boot
Hi Jagan,
> -----Original Message-----
> From: Jagan Teki <jagan@amarulasolutions.com>
> Sent: Monday, April 20, 2020 9:58 PM
> To: Sagar Kadam <sagar.kadam@sifive.com>
> Cc: Vignesh R <vigneshr@ti.com>; u-boot at lists.denx.de; Bin Meng
> <bmeng.cn@gmail.com>; linux-amarula at amarulasolutions.com
> Subject: Re: [PATCH 1/2] mtd: spi-nor: Enable QE bit for ISSI flash
>
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
>
> On Mon, Apr 20, 2020 at 9:56 PM Sagar Kadam <sagar.kadam@sifive.com>
> wrote:
> >
> > Hi Jagan,
> >
> > > -----Original Message-----
> > > From: Jagan Teki <jagan@amarulasolutions.com>
> > > Sent: Monday, April 20, 2020 3:36 PM
> > > To: Vignesh R <vigneshr@ti.com>; u-boot at lists.denx.de
> > > Cc: Bin Meng <bmeng.cn@gmail.com>; linux-
> > > amarula at amarulasolutions.com; Jagan Teki
> > > <jagan@amarulasolutions.com>; Sagar Kadam
> <sagar.kadam@sifive.com>
> > > Subject: [PATCH 1/2] mtd: spi-nor: Enable QE bit for ISSI flash
> > >
> > > [External Email] Do not click links or attachments unless you
> > > recognize the sender and know the content is safe
> > >
> > > Enable QE bit for ISSI flash chips.
> > >
> > > QE enablement logic is similar to what Micromax has, so reuse the
> > > existing code itself.
> >
> > nits: s/Micromax/Macronix
>
> Will update while applying, thanks.
Sure, no issues.
Thanks & BR,
Sagar Kadam
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-04-20 19:17 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-04-20 10:06 [PATCH 1/2] mtd: spi-nor: Enable QE bit for ISSI flash Jagan Teki
2020-04-20 10:06 ` [PATCH 2/2] mtd: spi-nor-ids: Enable 4B_OPCODES for is25wp256 Jagan Teki
2020-04-20 16:31 ` Sagar Kadam
2020-04-20 16:26 ` [PATCH 1/2] mtd: spi-nor: Enable QE bit for ISSI flash Sagar Kadam
2020-04-20 16:27 ` Jagan Teki
2020-04-20 19:17 ` Sagar Kadam
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