Re: [PATCH 4/8] clk: rk3399: Disable PCIE_PHY clock【请注意，邮件由linux-rockchip-bounces+kever.yang=rock-chips.com@lists.infradead.org代发】

Kever Yang
2020-04-28T09:53:31Z

On 2020/4/25 ??7:03, Jagan Teki wrote:
> Add PCIE_PHY clock disablement support on rk3399
> clock driver.
>
> This would trigger if the PCIe PHY driver failed to
> initialize or power on the PHY.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
> drivers/clk/rockchip/clk_rk3399.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index 8e069fbade..2d447f96f7 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -1085,6 +1085,22 @@ static int rk3399_clk_enable(struct clk *clk)
> return 0;
> }
>
> +static int rk3399_clk_disable(struct clk *clk)
> +{
> + struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
> +
> + switch (clk->id) {
> + case SCLK_PCIEPHY_REF:
> + rk_clrreg(&priv->cru->clksel_con[18], BIT(7));
> + break;
> + default:
> + debug("%s: unsupported clk %ld\n", __func__, clk->id);
> + return -ENOENT;
> + }
> +
> + return 0;
> +}
> +
> static struct clk_ops rk3399_clk_ops = {
> .get_rate = rk3399_clk_get_rate,
> .set_rate = rk3399_clk_set_rate,
> @@ -1092,6 +1108,7 @@ static struct clk_ops rk3399_clk_ops = {
> .set_parent = rk3399_clk_set_parent,
> #endif
> .enable = rk3399_clk_enable,
> + .disable = rk3399_clk_disable,
> };
>
> #ifdef CONFIG_SPL_BUILD