[PATCH] arm: dts: imx8mm: sync dts from Linux Kernel 5.6.7

sbabic at denx.de
2020-05-01T16:32:10Z

> This patch synchronizes the device tree with that from 5.6.7.
> This also adds nodes for crypto and ddrc, which makes keeping
> the device tree files from individual boards in sync with the
> Linux kernel. This is helpful when boads reference those nodes.
> Signed-off-by: Adam Ford <aford173@gmail.com>
> diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
> index 8aafad2449..1e5e11592f 100644
> --- a/arch/arm/dts/imx8mm.dtsi
> +++ b/arch/arm/dts/imx8mm.dtsi
> @@ -12,7 +12,6 @@
> #include "imx8mm-pinfunc.h"
>
> / {
> - compatible = "fsl,imx8mm";
> interrupt-parent = <&gic>;
> #address-cells = <2>;
> #size-cells = <2>;
> @@ -141,11 +140,6 @@
> };
> };
>
> - memory at 40000000 {
> - device_type = "memory";
> - reg = <0x0 0x40000000 0 0x80000000>;
> - };
> -
> osc_32k: clock-osc-32k {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -233,7 +227,7 @@
> ranges = <0x0 0x0 0x0 0x3e000000>;
>
> aips1: bus at 30000000 {
> - compatible = "fsl,aips-bus", "simple-bus";
> + compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0x30000000 0x30000000 0x400000>;
> @@ -394,7 +388,7 @@
> };
>
> sdma2: dma-controller at 302c0000 {
> - compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
> + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
> reg = <0x302c0000 0x10000>;
> interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
> @@ -405,7 +399,7 @@
> };
>
> sdma3: dma-controller at 302b0000 {
> - compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
> + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
> reg = <0x302b0000 0x10000>;
> interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
> @@ -439,7 +433,7 @@
> };
>
> anatop: anatop at 30360000 {
> - compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus";
> + compatible = "fsl,imx8mm-anatop", "syscon";
> reg = <0x30360000 0x10000>;
> };
>
> @@ -479,14 +473,18 @@
> <&clk IMX8MM_CLK_AUDIO_AHB>,
> <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
> <&clk IMX8MM_SYS_PLL3>,
> - <&clk IMX8MM_VIDEO_PLL1>;
> + <&clk IMX8MM_VIDEO_PLL1>,
> + <&clk IMX8MM_AUDIO_PLL1>,
> + <&clk IMX8MM_AUDIO_PLL2>;
> assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
> <&clk IMX8MM_SYS_PLL1_800M>;
> assigned-clock-rates = <0>,
> <400000000>,
> <400000000>,
> <750000000>,
> - <594000000>;
> + <594000000>,
> + <393216000>,
> + <361267200>;
> };
>
> src: reset-controller at 30390000 {
> @@ -498,7 +496,7 @@
> };
>
> aips2: bus at 30400000 {
> - compatible = "fsl,aips-bus", "simple-bus";
> + compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0x30400000 0x30400000 0x400000>;
> @@ -557,7 +555,7 @@
> };
>
> aips3: bus at 30800000 {
> - compatible = "fsl,aips-bus", "simple-bus";
> + compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0x30800000 0x30800000 0x400000>;
> @@ -638,6 +636,36 @@
> status = "disabled";
> };
>
> + crypto: crypto at 30900000 {
> + compatible = "fsl,sec-v4.0";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x30900000 0x40000>;
> + ranges = <0 0x30900000 0x40000>;
> + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_AHB>,
> + <&clk IMX8MM_CLK_IPG_ROOT>;
> + clock-names = "aclk", "ipg";
> +
> + sec_jr0: jr at 1000 {
> + compatible = "fsl,sec-v4.0-job-ring";
> + reg = <0x1000 0x1000>;
> + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + sec_jr1: jr at 2000 {
> + compatible = "fsl,sec-v4.0-job-ring";
> + reg = <0x2000 0x1000>;
> + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + sec_jr2: jr at 3000 {
> + compatible = "fsl,sec-v4.0-job-ring";
> + reg = <0x3000 0x1000>;
> + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> i2c1: i2c at 30a20000 {
> compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
> #address-cells = <1>;
> @@ -698,8 +726,6 @@
> <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
> <&clk IMX8MM_CLK_USDHC1_ROOT>;
> clock-names = "ipg", "ahb", "per";
> - assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
> - assigned-clock-rates = <400000000>;
> fsl,tuning-start-tap = <20>;
> fsl,tuning-step= <2>;
> bus-width = <4>;
> @@ -728,8 +754,6 @@
> <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
> <&clk IMX8MM_CLK_USDHC3_ROOT>;
> clock-names = "ipg", "ahb", "per";
> - assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
> - assigned-clock-rates = <400000000>;
> fsl,tuning-start-tap = <20>;
> fsl,tuning-step= <2>;
> bus-width = <4>;
> @@ -737,11 +761,11 @@
> };
>
> sdma1: dma-controller at 30bd0000 {
> - compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
> + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
> reg = <0x30bd0000 0x10000>;
> interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
> - <&clk IMX8MM_CLK_SDMA1_ROOT>;
> + <&clk IMX8MM_CLK_AHB>;
> clock-names = "ipg", "ahb";
> #dma-cells = <3>;
> fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
> @@ -776,7 +800,7 @@
> };
>
> aips4: bus at 32c00000 {
> - compatible = "fsl,aips-bus", "simple-bus";
> + compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0x32c00000 0x32c00000 0x400000>;
> @@ -859,6 +883,16 @@
> interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + ddrc: memory-controller at 3d400000 {
> + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
> + reg = <0x3d400000 0x400000>;
> + clock-names = "core", "pll", "alt", "apb";
> + clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
> + <&clk IMX8MM_DRAM_PLL>,
> + <&clk IMX8MM_CLK_DRAM_ALT>,
> + <&clk IMX8MM_CLK_DRAM_APB>;
> + };
> +
> ddr-pmu at 3d800000 {
> compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
> reg = <0x3d800000 0x400000>;
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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