[PATCH v2 5/5] board: apalis_imx6: Add KSZ9131 phy skew settings

[sbabic at denx.de <sbabic@denx.de>]

> This patch adds skew register settings for KSZ9131. It checks first
> which phy is on the board and then applies the correct skew settings.
> Skew settings calculation for the KSZ9131:
> The i.MX6 SoC has an output skew tolerance of -100ps to 900ps. All
> PCB traces where routed exactly the same length so we can calculate
> the skew settings without taking the length into consideration. The
> traces are all length matched.
> RXC skew (PHY to MAC):
> - We use the 2ns DLL controlled delay on the PHY
> - We do not use the skew registers
> This results in the following values:
> 		RXC
> PHY fixed Delay	2000ps
> PHY Added Delay	0ps
> T_setup_R min	2.00ns
> T_setup_R typ	2.00ns
> T_setup_R max	2.00ns
> T_hold_R min	1.60ns
> T_hold_R typ	2.00ns
> T_hold_R max	2.40ns
> That means we are well within RGMII specs.
> TXC skew (MAC to PHY):
> - We use the 2ns DLL controlled delay on the PHY
> - We then subtract ~0.6ns with TXD[0:3] and TXC clock pad skew
>   register in a resulting ~1.4ns delay.
> This results in the following values under consideration of the
> tolerances:
> 		TXC min	TXC typ	TXC max
> MAC min		-100ps	-100ps	-100ps
> MAC max		900ps	900ps	900ps
> PHY fixed Delay	2000ps	2000ps	2000ps
> PHY added Delay	-340ps	-600ps	-859ps
> T_setup_T min	1.56ns	1.30ns	1.04ns
> T_setup_T typ	2.06ns	1.80ns	1.54ns
> T_setup_T max	2.56ns	2.30ns	2.04ns
> T_hold_T min	1.04ns	1.30ns	1.56ns
> T_hold_T typ	1.94ns	2.20ns	2.46ns
> T_hold_T max	2.84ns	3.10ns	3.36ns
> This shows that T_hold_T min and T_setup_T min times are out of spec
> for RGMII timing. However the KSZ9131 has a minimal value for this time
> of 0.8ns which is met under all circumstances.
> Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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