From: Michael Walle <michael@walle.cc>
To: u-boot@lists.denx.de
Subject: [PATCH v4 02/12] phy: atheros: Use common functions for RGMII internal delays
Date: Thu, 7 May 2020 00:11:49 +0200 [thread overview]
Message-ID: <20200506221159.1298-3-michael@walle.cc> (raw)
In-Reply-To: <20200506221159.1298-1-michael@walle.cc>
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
drivers/net/phy/atheros.c | 69 +++++++++++++++++++++++----------------
1 file changed, 41 insertions(+), 28 deletions(-)
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 537c1a9125..c0c2b4db39 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -12,16 +12,45 @@
#define AR803x_PHY_DEBUG_DATA_REG 0x1e
#define AR803x_DEBUG_REG_5 0x5
-#define AR803x_RGMII_TX_CLK_DLY 0x100
+#define AR803x_RGMII_TX_CLK_DLY BIT(8)
#define AR803x_DEBUG_REG_0 0x0
-#define AR803x_RGMII_RX_CLK_DLY 0x8000
+#define AR803x_RGMII_RX_CLK_DLY BIT(15)
+
+static void ar803x_enable_rx_delay(struct phy_device *phydev, bool on)
+{
+ int regval;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
+ AR803x_DEBUG_REG_0);
+ regval = phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG);
+ if (on)
+ regval |= AR803x_RGMII_RX_CLK_DLY;
+ else
+ regval &= ~AR803x_RGMII_RX_CLK_DLY;
+ phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, regval);
+}
+
+static void ar803x_enable_tx_delay(struct phy_device *phydev, bool on)
+{
+ int regval;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
+ AR803x_DEBUG_REG_5);
+ regval = phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG);
+ if (on)
+ regval |= AR803x_RGMII_TX_CLK_DLY;
+ else
+ regval &= ~AR803x_RGMII_TX_CLK_DLY;
+ phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, regval);
+}
static int ar8021_config(struct phy_device *phydev)
{
phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
+ phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
+ AR803x_DEBUG_REG_5);
+ phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, 0x3D47);
phydev->supported = phydev->drv->features;
return 0;
@@ -30,20 +59,12 @@ static int ar8021_config(struct phy_device *phydev)
static int ar8031_config(struct phy_device *phydev)
{
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
- phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
- phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
- AR803x_DEBUG_REG_5);
- phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
- AR803x_RGMII_TX_CLK_DLY);
- }
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+ ar803x_enable_tx_delay(phydev, true);
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
- phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
- phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
- AR803x_DEBUG_REG_0);
- phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
- AR803x_RGMII_RX_CLK_DLY);
- }
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+ ar803x_enable_rx_delay(phydev, true);
phydev->supported = phydev->drv->features;
@@ -64,20 +85,12 @@ static int ar8035_config(struct phy_device *phydev)
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018));
if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
- (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
- /* select debug reg 5 */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x5);
- /* enable tx delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x0100);
- }
+ (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
+ ar803x_enable_tx_delay(phydev, true);
if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
- (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) {
- /* select debug reg 0 */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x0);
- /* enable rx delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x8000);
- }
+ (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
+ ar803x_enable_rx_delay(phydev, true);
phydev->supported = phydev->drv->features;
--
2.20.1
next prev parent reply other threads:[~2020-05-06 22:11 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-06 22:11 [PATCH v4 00/12] phy: atheros: dt bindings and cleanup Michael Walle
2020-05-06 22:11 ` [PATCH v4 01/12] phy: atheros: Make RGMII Tx delays actually configurable for AR8035 Michael Walle
2020-05-07 18:51 ` Tom Rini
2020-05-06 22:11 ` Michael Walle [this message]
2020-05-07 18:52 ` [PATCH v4 02/12] phy: atheros: Use common functions for RGMII internal delays Tom Rini
2020-05-06 22:11 ` [PATCH v4 03/12] phy: atheros: Clarify the configuration of the CLK_25M output pin Michael Walle
2020-05-07 18:52 ` Tom Rini
2020-05-06 22:11 ` [PATCH v4 04/12] phy: atheros: Explicitly disable RGMII delays Michael Walle
2020-05-07 18:52 ` Tom Rini
2020-05-06 22:11 ` [PATCH v4 05/12] phy: atheros: Clarify the intention of ar8021_config Michael Walle
2020-05-07 18:52 ` Tom Rini
2020-05-06 22:11 ` [PATCH v4 06/12] phy: atheros: fix AR8021 PHY ID mask Michael Walle
2020-05-07 18:53 ` Tom Rini
2020-05-06 22:11 ` [PATCH v4 07/12] phy: atheros: use defines for PHY IDs Michael Walle
2020-05-07 18:53 ` Tom Rini
2020-05-06 22:11 ` [PATCH v4 08/12] phy: atheros: introduce debug read and write functions Michael Walle
2020-05-07 18:53 ` Tom Rini
2020-05-06 22:11 ` [PATCH v4 09/12] phy: atheros: move delay config to common function Michael Walle
2020-05-07 18:53 ` Tom Rini
2020-05-06 22:11 ` [PATCH v4 10/12] phy: atheros: add device tree bindings and config Michael Walle
2020-05-07 18:53 ` Tom Rini
2020-05-06 22:11 ` [PATCH v4 11/12] phy: atheros: ar8035: remove static clock config Michael Walle
2020-05-07 18:53 ` Tom Rini
2020-05-06 22:11 ` [PATCH v4 12/12] phy: atheros: consolidate {ar8031|ar8035}_config() Michael Walle
2020-05-07 18:53 ` Tom Rini
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