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From: Stefan Roese <sr@denx.de>
To: u-boot@lists.denx.de
Subject: [PATCH v2 03/12] mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM
Date: Thu, 14 May 2020 11:59:03 +0200	[thread overview]
Message-ID: <20200514095912.14428-4-sr@denx.de> (raw)
In-Reply-To: <20200514095912.14428-1-sr@denx.de>

This patch enables the usage of CONFIG_MIPS_L2_CACHE without
CONFIG_MIPS_CM, which is what is needed for the newly added Octeon
platform.

Signed-off-by: Stefan Roese <sr@denx.de>

---

Changes in v2:
- Restructure patch by adding empty functions to asm/cm.h instead

 arch/mips/include/asm/cm.h | 12 ++++++++++++
 arch/mips/lib/cache.c      |  2 --
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/mips/include/asm/cm.h b/arch/mips/include/asm/cm.h
index 8f37471f81..06d721d228 100644
--- a/arch/mips/include/asm/cm.h
+++ b/arch/mips/include/asm/cm.h
@@ -40,6 +40,7 @@
 
 #include <asm/io.h>
 
+#if CONFIG_IS_ENABLED(MIPS_CM)
 static inline void *mips_cm_base(void)
 {
 	return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE);
@@ -55,6 +56,17 @@ static inline unsigned long mips_cm_l2_line_size(void)
 	line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0);
 	return line_sz ? (2 << line_sz) : 0;
 }
+#else
+static inline void *mips_cm_base(void)
+{
+	return NULL;
+}
+
+static inline unsigned long mips_cm_l2_line_size(void)
+{
+	return 0;
+}
+#endif
 
 #endif /* !__ASSEMBLY__ */
 
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 1a8c87d094..fdffe9493b 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -7,9 +7,7 @@
 #include <common.h>
 #include <cpu_func.h>
 #include <asm/cacheops.h>
-#ifdef CONFIG_MIPS_L2_CACHE
 #include <asm/cm.h>
-#endif
 #include <asm/io.h>
 #include <asm/mipsregs.h>
 #include <asm/system.h>
-- 
2.26.2

  parent reply	other threads:[~2020-05-14  9:59 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-14  9:59 [PATCH v2 00/12] mips: Add initial Octeon MIPS64 base support Stefan Roese
2020-05-14  9:59 ` [PATCH v2 01/12] mips: start.S: Add CONFIG_MIPS_INIT_JUMP_OFFSET Stefan Roese
2020-05-14  9:59 ` [PATCH v2 02/12] mips: start.S: Don't call mips_cache_reset() on ARCH_OCTEON Stefan Roese
2020-05-14  9:59 ` Stefan Roese [this message]
2020-06-05 15:29   ` [PATCH v2 03/12] mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM Daniel Schwierzeck
2020-05-14  9:59 ` [PATCH v2 04/12] mips: cache: Make flush_cache() weak to enable overwrite Stefan Roese
2020-06-05 15:29   ` Daniel Schwierzeck
2020-05-14  9:59 ` [PATCH v2 05/12] mips: time: Only compile the weak get_tbclk() when needed Stefan Roese
2020-06-05 15:29   ` Daniel Schwierzeck
2020-05-14  9:59 ` [PATCH v2 06/12] mips: traps: Set WG bit in EBase register on Octeon Stefan Roese
2020-06-05 15:30   ` Daniel Schwierzeck
2020-05-14  9:59 ` [PATCH v2 07/12] mips: mipsregs.h: Add more register macros for Octeon port Stefan Roese
2020-05-14  9:59 ` [PATCH v2 08/12] mips: mipsregs.h: Sync with linux v5.7.0-rc3 version Stefan Roese
2020-05-14  9:59 ` [PATCH v2 09/12] sysreset: Add Octeon sysreset driver Stefan Roese
2020-05-14  9:59 ` [PATCH v2 10/12] mips: octeon: Initial minimal support for the Marvell Octeon SoC Stefan Roese
2020-06-16 17:42   ` Daniel Schwierzeck
2020-06-19  8:08     ` Stefan Roese
2020-05-14  9:59 ` [PATCH v2 11/12] mips: octeon: dts: Add Octeon 3 cn73xx base dtsi file Stefan Roese
2020-05-14  9:59 ` [PATCH v2 12/12] mips: octeon: Add minimal Octeon 3 EBB7304 EVK support Stefan Roese
2020-06-16 17:35   ` Daniel Schwierzeck
2020-06-19  8:06     ` Stefan Roese
2020-05-26 12:23 ` [PATCH v2 00/12] mips: Add initial Octeon MIPS64 base support Stefan Roese
2020-06-02 10:59   ` Stefan Roese
2020-06-05 15:40     ` Daniel Schwierzeck
2020-06-06  5:25       ` Stefan Roese
2020-06-15  7:49         ` Stefan Roese
2020-06-16 17:27           ` Daniel Schwierzeck
2020-06-19  7:51             ` Stefan Roese

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