[PATCH v2 07/12] mips: mipsregs.h: Add more register macros for Octeon port

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From: Stefan Roese <sr@denx.de>
To: u-boot@lists.denx.de
Subject: [PATCH v2 07/12] mips: mipsregs.h: Add more register macros for Octeon port
Date: Thu, 14 May 2020 11:59:07 +0200	[thread overview]
Message-ID: <20200514095912.14428-8-sr@denx.de> (raw)
In-Reply-To: <20200514095912.14428-1-sr@denx.de>

From: Aaron Williams <awilliams@marvell.com>

Thips patch adds some more register definitions which will be used by
the Octeon platform.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---

Changes in v2: None

 arch/mips/include/asm/mipsregs.h | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 998f84d0a1..5214b3197e 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -40,15 +40,20 @@
 #define CP0_CONF $3
 #define CP0_GLOBALNUMBER $3, 1
 #define CP0_CONTEXT $4
+#define CP0_USERLOCAL $4, 2
 #define CP0_PAGEMASK $5
+#define CP0_PAGEGRAIN $5, 1
 #define CP0_WIRED $6
 #define CP0_INFO $7
 #define CP0_HWRENA $7, 0
 #define CP0_BADVADDR $8
 #define CP0_BADINSTR $8, 1
 #define CP0_COUNT $9
+#define CP0_CVMCOUNT $9, 6
+#define CP0_CVMCTL $9, 7
 #define CP0_ENTRYHI $10
 #define CP0_COMPARE $11
+#define CP0_CVMMEMCTL $11, 7
 #define CP0_STATUS $12
 #define CP0_CAUSE $13
 #define CP0_EPC $14
@@ -56,8 +61,11 @@
 #define CP0_EBASE $15, 1
 #define CP0_CMGCRBASE $15, 3
 #define CP0_CONFIG $16
+#define CP0_CONFIG1 $16, 1
 #define CP0_CONFIG3 $16, 3
+#define CP0_CONFIG4 $16, 4
 #define CP0_CONFIG5 $16, 5
+#define CP0_CVMMEMCTL2 $16, 6
 #define CP0_LLADDR $17
 #define CP0_WATCHLO $18
 #define CP0_WATCHHI $19
@@ -67,13 +75,22 @@
 #define CP0_DEBUG $23
 #define CP0_DEPC $24
 #define CP0_PERFORMANCE $25
+#define CP0_PERF_CNT0 $25, 1
+#define CP0_PERF_CNT1 $25, 3
+#define CP0_PERF_CNT2 $25, 5
+#define CP0_PERF_CNT3 $25, 7
 #define CP0_ECC $26
 #define CP0_CACHEERR $27
+#define CP0_CACHEERR_ICACHE $27
+#define CP0_CACHEERR_DCACHE $27, 1
 #define CP0_TAGLO $28
 #define CP0_TAGHI $29
 #define CP0_ERROREPC $30
 #define CP0_DESAVE $31
-
+#define CP0_KSCRATCH1 $31, 2
+#define CP0_KSCRATCH2 $31, 3
+#define CP0_KSCRATCH3 $31, 4
+#define CP0_KSCRATCH4 $31, 5
 /*
  * R4640/R4650 cp0 register names.  These registers are listed
  * here only for completeness; without MMU these CPUs are not useable
-- 
2.26.2

next prev parent reply	other threads:[~2020-05-14  9:59 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-14  9:59 [PATCH v2 00/12] mips: Add initial Octeon MIPS64 base support Stefan Roese
2020-05-14  9:59 ` [PATCH v2 01/12] mips: start.S: Add CONFIG_MIPS_INIT_JUMP_OFFSET Stefan Roese
2020-05-14  9:59 ` [PATCH v2 02/12] mips: start.S: Don't call mips_cache_reset() on ARCH_OCTEON Stefan Roese
2020-05-14  9:59 ` [PATCH v2 03/12] mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM Stefan Roese
2020-06-05 15:29   ` Daniel Schwierzeck
2020-05-14  9:59 ` [PATCH v2 04/12] mips: cache: Make flush_cache() weak to enable overwrite Stefan Roese
2020-06-05 15:29   ` Daniel Schwierzeck
2020-05-14  9:59 ` [PATCH v2 05/12] mips: time: Only compile the weak get_tbclk() when needed Stefan Roese
2020-06-05 15:29   ` Daniel Schwierzeck
2020-05-14  9:59 ` [PATCH v2 06/12] mips: traps: Set WG bit in EBase register on Octeon Stefan Roese
2020-06-05 15:30   ` Daniel Schwierzeck
2020-05-14  9:59 ` Stefan Roese [this message]
2020-05-14  9:59 ` [PATCH v2 08/12] mips: mipsregs.h: Sync with linux v5.7.0-rc3 version Stefan Roese
2020-05-14  9:59 ` [PATCH v2 09/12] sysreset: Add Octeon sysreset driver Stefan Roese
2020-05-14  9:59 ` [PATCH v2 10/12] mips: octeon: Initial minimal support for the Marvell Octeon SoC Stefan Roese
2020-06-16 17:42   ` Daniel Schwierzeck
2020-06-19  8:08     ` Stefan Roese
2020-05-14  9:59 ` [PATCH v2 11/12] mips: octeon: dts: Add Octeon 3 cn73xx base dtsi file Stefan Roese
2020-05-14  9:59 ` [PATCH v2 12/12] mips: octeon: Add minimal Octeon 3 EBB7304 EVK support Stefan Roese
2020-06-16 17:35   ` Daniel Schwierzeck
2020-06-19  8:06     ` Stefan Roese
2020-05-26 12:23 ` [PATCH v2 00/12] mips: Add initial Octeon MIPS64 base support Stefan Roese
2020-06-02 10:59   ` Stefan Roese
2020-06-05 15:40     ` Daniel Schwierzeck
2020-06-06  5:25       ` Stefan Roese
2020-06-15  7:49         ` Stefan Roese
2020-06-16 17:27           ` Daniel Schwierzeck
2020-06-19  7:51             ` Stefan Roese

find likely ancestor, descendant, or conflicting patches for this message:
( dfblob:998f84d0a dfblob:5214b3197 )
 OR (
bs:"[PATCH v2 07/12] mips: mipsregs.h: Add more register macros for Octeon port" )
	(help)

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