[PATCH v3 1/4] phy: atheros: ar8035: Fix clock output calculation

[PATCH v3 1/4] phy: atheros: ar8035: Fix clock output calculation

[Fabio Estevam]

The clock ouput frequency is calculated incorrectly for AR8035 due to
wrong masking of priv->clk_25m_reg and priv->clk_25m_mask.

This same issue has been already fixed in the kernel by:

commit b1f4c209d84057b6d40b939b6e4404854271d797
Author: Oleksij Rempel <o.rempel@pengutronix.de>
Date:   Wed Apr 1 11:57:32 2020 +0200

    net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035

    The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set
    for the values that comprise the fields, not zero-bits-set.

    This patch fixes the clock frequency configuration for ATH8030 and
    ATH8035 Atheros PHYs by removing the erroneous "~".

    To reproduce this bug, configure the PHY  with the device tree binding
    "qca,clk-out-frequency" and remove the machine specific PHY fixups.

    Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding")
    Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
    Reported-by: Russell King <rmk+kernel@armlinux.org.uk>
    Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk>
    Tested-by: Russell King <rmk+kernel@armlinux.org.uk>
    Signed-off-by: David S. Miller <davem@davemloft.net>

Apply the same fix in the U-Boot driver.

Tested on a i.MX6 Hummingboard.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Tested-by: Tom Rini <trini@konsulko.com>
---
Changes since v2:
- None

 drivers/net/phy/atheros.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 13f7275d17..f922fecd6b 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -275,11 +275,10 @@ static int ar803x_of_init(struct phy_device *phydev)
 		 * Fixup for the AR8035 which only has two bits. The two
 		 * remaining bits map to the same frequencies.
 		 */
-		if (phydev->drv->uid == AR8035_PHY_ID) {
-			u16 clear = AR803x_CLK_25M_MASK & AR8035_CLK_25M_MASK;
 
-			priv->clk_25m_mask &= ~clear;
-			priv->clk_25m_reg &= ~clear;
+		if (phydev->drv->uid == AR8035_PHY_ID) {
+			priv->clk_25m_reg &= AR8035_CLK_25M_MASK;
+			priv->clk_25m_mask &= AR8035_CLK_25M_MASK;
 		}
 	}
 
-- 
2.17.1

[PATCH v3 2/4] net: fec: Allow the PHY node to be retrieved

[Fabio Estevam]

As we move towards driver model, it is required to let the FEC driver
know how to properly deal with an Ethernet PHY subnode in the device tree.

For example:

 &fec {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
	phy-handle = <&phy>;
 	phy-mode = "rgmii-id";
 	phy-reset-duration = <2>;
 	phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
 	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		phy: ethernet-phy at 0 {
			reg = <0>;
			qca,clk-out-frequency = <125000000>;
		};
	};
 };

Currently the PHY node pointer is incorrectly associated with the
Ethernel controller instead of the PHY node itself. 

This causes the PHY properties, such as "qca,clk-out-frequency" in
the example above to not get parsed.

Fix this problem by populating the phy_of_node node.

Suggested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Tom Rini <trini@konsulko.com>
---
Changes since v2:
- None

 drivers/net/fec_mxc.c | 7 +++++--
 drivers/net/fec_mxc.h | 1 +
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 9ae2db033e..992180df86 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1294,7 +1294,7 @@ static const struct eth_ops fecmxc_ops = {
 	.read_rom_hwaddr	= fecmxc_read_rom_hwaddr,
 };
 
-static int device_get_phy_addr(struct udevice *dev)
+static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev)
 {
 	struct ofnode_phandle_args phandle_args;
 	int reg;
@@ -1305,6 +1305,8 @@ static int device_get_phy_addr(struct udevice *dev)
 		return -ENODEV;
 	}
 
+	priv->phy_of_node = phandle_args.node;
+
 	reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
 
 	return reg;
@@ -1315,7 +1317,7 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
 	struct phy_device *phydev;
 	int addr;
 
-	addr = device_get_phy_addr(dev);
+	addr = device_get_phy_addr(priv, dev);
 #ifdef CONFIG_FEC_MXC_PHYADDR
 	addr = CONFIG_FEC_MXC_PHYADDR;
 #endif
@@ -1325,6 +1327,7 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
 		return -ENODEV;
 
 	priv->phydev = phydev;
+	priv->phydev->node = priv->phy_of_node;
 	phy_config(phydev);
 
 	return 0;
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 0e8f08a51a..659d62646f 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -250,6 +250,7 @@ struct fec_priv {
 	struct mii_dev *bus;
 #ifdef CONFIG_PHYLIB
 	struct phy_device *phydev;
+	ofnode phy_of_node;
 #else
 	int phy_id;
 	int (*mii_postcall)(int);
-- 
2.17.1

[PATCH v3 3/4] ARM: dts: imx6qdl-sr-som: Sync with kernel 5.8-rc1

[Fabio Estevam]

Sync the device tree with 5.8-rc1.

It basically contains the following extra kernel commit:

commit 86b08bd5b99480b79a25343f24c1b8c4ddcb5c09
Author: Russell King <rmk+kernel@armlinux.org.uk>
Date:   Wed Apr 15 16:44:17 2020 +0100

    ARM: dts: imx6-sr-som: add ethernet PHY configuration

    Add ethernet PHY configuration ahead of removing the quirk that
    configures the clocking mode for the PHY.  The RGMII delay is
    already set correctly.

    Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
    Reviewed-by: Fabio Estevam <festevam@gmail.com>
    Signed-off-by: Shawn Guo <shawnguo@kernel.org>

, which passes the 'qca,clk-out-frequency' property and it is important
to specify the correct frequency generated by the AR8035.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Tom Rini <trini@konsulko.com>
---
Changes since v2:
- Change from AR8031 to AR8035, as cubox uses AR8035 

 arch/arm/dts/imx6qdl-sr-som.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/dts/imx6qdl-sr-som.dtsi b/arch/arm/dts/imx6qdl-sr-som.dtsi
index 6d7f6b9035..b06577808f 100644
--- a/arch/arm/dts/imx6qdl-sr-som.dtsi
+++ b/arch/arm/dts/imx6qdl-sr-som.dtsi
@@ -53,10 +53,21 @@
 &fec {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
+	phy-handle = <&phy>;
 	phy-mode = "rgmii-id";
 	phy-reset-duration = <2>;
 	phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
 	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy: ethernet-phy at 0 {
+			reg = <0>;
+			qca,clk-out-frequency = <125000000>;
+		};
+	};
 };
 
 &iomuxc {
-- 
2.17.1

[PATCH v3 4/4] mx6cuboxi: Convert to DM_ETH

[Fabio Estevam]

Migration to DM_ETH is mandatory, so convert mx6cuboxi to Ethernet
Driver Model.

This also brings the benefit of restoring Ethernet functionality.

Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Tom Rini <trini@konsulko.com>
---
Changes since v2:
- Removed extra Signed-off-by

 board/solidrun/mx6cuboxi/mx6cuboxi.c | 134 ++++-----------------------
 configs/mx6cuboxi_defconfig          |   3 +
 include/configs/mx6cuboxi.h          |   6 --
 3 files changed, 20 insertions(+), 123 deletions(-)

diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 94707bccb2..59e8b1dca1 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -17,7 +17,6 @@
 #include <image.h>
 #include <init.h>
 #include <log.h>
-#include <net.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
@@ -33,8 +32,6 @@
 #include <mmc.h>
 #include <fsl_esdhc_imx.h>
 #include <malloc.h>
-#include <miiphy.h>
-#include <netdev.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
@@ -52,16 +49,6 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |		\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define ETH_PHY_RESET	IMX_GPIO_NR(4, 15)
 #define USB_H1_VBUS	IMX_GPIO_NR(1, 0)
 
 enum board_type {
@@ -237,110 +224,6 @@ int board_mmc_init(bd_t *bis)
 	return 0;
 }
 
-static iomux_v3_cfg_t const enet_pads[] = {
-	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	/* AR8035 reset */
-	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
-	/* AR8035 interrupt */
-	IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-	/* GPIO16 -> AR8035 25MHz */
-	IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK	  | MUX_PAD_CTRL(NO_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC	  | MUX_PAD_CTRL(NO_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
-	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)),
-	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
-	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
-	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
-	IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
-	IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
-};
-
-static void setup_iomux_enet(void)
-{
-	struct gpio_desc desc;
-	int ret;
-
-	SETUP_IOMUX_PADS(enet_pads);
-
-	ret = dm_gpio_lookup_name("GPIO4_15", &desc);
-	if (ret) {
-		printf("%s: phy reset lookup failed\n", __func__);
-		return;
-	}
-
-	ret = dm_gpio_request(&desc, "phy-reset");
-	if (ret) {
-		printf("%s: phy reset request failed\n", __func__);
-		return;
-	}
-
-	gpio_direction_output(ETH_PHY_RESET, 0);
-	mdelay(10);
-	gpio_set_value(ETH_PHY_RESET, 1);
-	udelay(100);
-
-	gpio_free_list_nodev(&desc, 1);
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
-/* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */
-#define ETH_PHY_MASK	((1 << 0x0) | (1 << 0x4))
-
-int board_eth_init(bd_t *bis)
-{
-	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	struct mii_dev *bus;
-	struct phy_device *phydev;
-
-	int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
-	if (ret)
-		return ret;
-
-	/* set gpr1[ENET_CLK_SEL] */
-	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
-
-	setup_iomux_enet();
-
-	bus = fec_get_miibus(IMX_FEC_BASE, -1);
-	if (!bus)
-		return -EINVAL;
-
-	phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII);
-	if (!phydev) {
-		ret = -EINVAL;
-		goto free_bus;
-	}
-
-	debug("using phy at address %d\n", phydev->addr);
-	ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
-	if (ret)
-		goto free_phydev;
-
-	return 0;
-
-free_phydev:
-	free(phydev);
-free_bus:
-	free(bus);
-	return ret;
-}
-
 #ifdef CONFIG_VIDEO_IPUV3
 static void do_enable_hdmi(struct display_info_t const *dev)
 {
@@ -433,6 +316,21 @@ static int setup_display(void)
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
 
+static int setup_fec(void)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+
+	ret = enable_fec_anatop_clock(0, ENET_25MHZ);
+	if (ret)
+		return ret;
+
+	/* set gpr1[ENET_CLK_SEL] */
+	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+
+	return 0;
+}
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -440,6 +338,8 @@ int board_early_init_f(void)
 #ifdef CONFIG_CMD_SATA
 	setup_sata();
 #endif
+	setup_fec();
+
 	return 0;
 }
 
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index df7e4611a0..568cfce4c0 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -50,6 +50,9 @@ CONFIG_DM_MMC=y
 CONFIG_FSL_USDHC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index 2ccf44e573..96f79e6b58 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -29,12 +29,6 @@
 #define CONFIG_LBA48
 #endif
 
-/* Ethernet Configuration */
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE			ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE		RGMII
-#define CONFIG_FEC_MXC_PHYADDR		0
-
 /* Framebuffer */
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
-- 
2.17.1

[PATCH v3 3/4] ARM: dts: imx6qdl-sr-som: Sync with kernel 5.8-rc1

[sbabic at denx.de]

> Sync the device tree with 5.8-rc1.
> It basically contains the following extra kernel commit:
> commit 86b08bd5b99480b79a25343f24c1b8c4ddcb5c09
> Author: Russell King <rmk+kernel@armlinux.org.uk>
> Date:   Wed Apr 15 16:44:17 2020 +0100
>     ARM: dts: imx6-sr-som: add ethernet PHY configuration
>     Add ethernet PHY configuration ahead of removing the quirk that
>     configures the clocking mode for the PHY.  The RGMII delay is
>     already set correctly.
>     Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
>     Reviewed-by: Fabio Estevam <festevam@gmail.com>
>     Signed-off-by: Shawn Guo <shawnguo@kernel.org>
> , which passes the 'qca,clk-out-frequency' property and it is important
> to specify the correct frequency generated by the AR8035.
> Signed-off-by: Fabio Estevam <festevam@gmail.com>
> Tested-by: Tom Rini <trini@konsulko.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[PATCH v3 4/4] mx6cuboxi: Convert to DM_ETH

[sbabic at denx.de]

> Migration to DM_ETH is mandatory, so convert mx6cuboxi to Ethernet
> Driver Model.
> This also brings the benefit of restoring Ethernet functionality.
> Reported-by: Tom Rini <trini@konsulko.com>
> Signed-off-by: Fabio Estevam <festevam@gmail.com>
> Tested-by: Tom Rini <trini@konsulko.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[PATCH v3 1/4] phy: atheros: ar8035: Fix clock output calculation

[sbabic at denx.de]

> The clock ouput frequency is calculated incorrectly for AR8035 due to
> wrong masking of priv->clk_25m_reg and priv->clk_25m_mask.
> This same issue has been already fixed in the kernel by:
> commit b1f4c209d84057b6d40b939b6e4404854271d797
> Author: Oleksij Rempel <o.rempel@pengutronix.de>
> Date:   Wed Apr 1 11:57:32 2020 +0200
>     net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035
>     The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set
>     for the values that comprise the fields, not zero-bits-set.
>     This patch fixes the clock frequency configuration for ATH8030 and
>     ATH8035 Atheros PHYs by removing the erroneous "~".
>     To reproduce this bug, configure the PHY  with the device tree binding
>     "qca,clk-out-frequency" and remove the machine specific PHY fixups.
>     Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding")
>     Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
>     Reported-by: Russell King <rmk+kernel@armlinux.org.uk>
>     Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk>
>     Tested-by: Russell King <rmk+kernel@armlinux.org.uk>
>     Signed-off-by: David S. Miller <davem@davemloft.net>
> Apply the same fix in the U-Boot driver.
> Tested on a i.MX6 Hummingboard.
> Signed-off-by: Fabio Estevam <festevam@gmail.com>
> Reviewed-by: Michael Walle <michael@walle.cc>
> Tested-by: Tom Rini <trini@konsulko.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[PATCH v3 2/4] net: fec: Allow the PHY node to be retrieved

[sbabic at denx.de]

> As we move towards driver model, it is required to let the FEC driver
> know how to properly deal with an Ethernet PHY subnode in the device tree.
> For example:
>  &fec {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
> 	phy-handle = <&phy>;
>  	phy-mode = "rgmii-id";
>  	phy-reset-duration = <2>;
>  	phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
>  	status = "okay";
> 	mdio {
> 		#address-cells = <1>;
> 		#size-cells = <0>;
> 		phy: ethernet-phy at 0 {
> 			reg = <0>;
> 			qca,clk-out-frequency = <125000000>;
> 		};
> 	};
>  };
> Currently the PHY node pointer is incorrectly associated with the
> Ethernel controller instead of the PHY node itself. 
> This causes the PHY properties, such as "qca,clk-out-frequency" in
> the example above to not get parsed.
> Fix this problem by populating the phy_of_node node.
> Suggested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> Signed-off-by: Fabio Estevam <festevam@gmail.com>
> Tested-by: Tom Rini <trini@konsulko.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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