From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Packham Date: Thu, 25 Jun 2020 12:48:50 +1200 Subject: [PATCH 1/2] arm: mvebu: a38x: Fix typo In-Reply-To: <20200625004851.21056-1-judge.packham@gmail.com> References: <20200625004851.21056-1-judge.packham@gmail.com> Message-ID: <20200625004851.21056-2-judge.packham@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Fix spelling of Alignment. Signed-off-by: Chris Packham --- arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index 67a00cf1cf7b..d4480622c89c 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -533,7 +533,7 @@ struct op_params pex_and_usb3_tx_config_params3[] = { struct op_params pex_by4_config_params[] = { /* unit_base_reg, unit_offset, mask, data, wait_time, num_of_loops */ {GLOBAL_CLK_SRC_HI, 0x800, 0x7, {0x5, 0x0, 0x0, 0x2}, 0, 0}, - /* Lane Alignement enable */ + /* Lane Alignment enable */ {LANE_ALIGN_REG0, 0x800, 0x1000, {0x0, 0x0, 0x0, 0x0}, 0, 0}, /* Max PLL phy config */ {CALIBRATION_CTRL_REG, 0x800, 0x1000, {0x1000, 0x1000, 0x1000, 0x1000}, -- 2.27.0