* [PATCH 0/2] arm: mvebu: a38x: USB2 serdes changes @ 2020-06-25 0:48 Chris Packham 2020-06-25 0:48 ` [PATCH 1/2] arm: mvebu: a38x: Fix typo Chris Packham 2020-06-25 0:48 ` [PATCH 2/2] arm: mvebu: a38x: Adjust UTMI PHY parameters Chris Packham 0 siblings, 2 replies; 5+ messages in thread From: Chris Packham @ 2020-06-25 0:48 UTC (permalink / raw) To: u-boot While debugging this issue with Marvell I found the change that was made to Marvell's u-boot but doesn't appear to have made it upstream. We're in the process of checking the affect it has on the USB compliance testing we're doing. I have regression tested it against a couple of USB devices (Ethernet and Storage). But it'd be good to get some more coverage against other hardware platforms and USB devices. Chris Packham (2): arm: mvebu: a38x: Fix typo arm: mvebu: a38x: Adjust UTMI PHY parameters .../serdes/a38x/high_speed_env_spec.c | 27 +++++++++++++++---- 1 file changed, 22 insertions(+), 5 deletions(-) -- 2.27.0 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] arm: mvebu: a38x: Fix typo 2020-06-25 0:48 [PATCH 0/2] arm: mvebu: a38x: USB2 serdes changes Chris Packham @ 2020-06-25 0:48 ` Chris Packham 2020-06-29 12:09 ` Stefan Roese 2020-06-25 0:48 ` [PATCH 2/2] arm: mvebu: a38x: Adjust UTMI PHY parameters Chris Packham 1 sibling, 1 reply; 5+ messages in thread From: Chris Packham @ 2020-06-25 0:48 UTC (permalink / raw) To: u-boot Fix spelling of Alignment. Signed-off-by: Chris Packham <judge.packham@gmail.com> --- arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index 67a00cf1cf7b..d4480622c89c 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -533,7 +533,7 @@ struct op_params pex_and_usb3_tx_config_params3[] = { struct op_params pex_by4_config_params[] = { /* unit_base_reg, unit_offset, mask, data, wait_time, num_of_loops */ {GLOBAL_CLK_SRC_HI, 0x800, 0x7, {0x5, 0x0, 0x0, 0x2}, 0, 0}, - /* Lane Alignement enable */ + /* Lane Alignment enable */ {LANE_ALIGN_REG0, 0x800, 0x1000, {0x0, 0x0, 0x0, 0x0}, 0, 0}, /* Max PLL phy config */ {CALIBRATION_CTRL_REG, 0x800, 0x1000, {0x1000, 0x1000, 0x1000, 0x1000}, -- 2.27.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 1/2] arm: mvebu: a38x: Fix typo 2020-06-25 0:48 ` [PATCH 1/2] arm: mvebu: a38x: Fix typo Chris Packham @ 2020-06-29 12:09 ` Stefan Roese 0 siblings, 0 replies; 5+ messages in thread From: Stefan Roese @ 2020-06-29 12:09 UTC (permalink / raw) To: u-boot On 25.06.20 02:48, Chris Packham wrote: > Fix spelling of Alignment. > > Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Thanks, Stefan > --- > > arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c > index 67a00cf1cf7b..d4480622c89c 100644 > --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c > +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c > @@ -533,7 +533,7 @@ struct op_params pex_and_usb3_tx_config_params3[] = { > struct op_params pex_by4_config_params[] = { > /* unit_base_reg, unit_offset, mask, data, wait_time, num_of_loops */ > {GLOBAL_CLK_SRC_HI, 0x800, 0x7, {0x5, 0x0, 0x0, 0x2}, 0, 0}, > - /* Lane Alignement enable */ > + /* Lane Alignment enable */ > {LANE_ALIGN_REG0, 0x800, 0x1000, {0x0, 0x0, 0x0, 0x0}, 0, 0}, > /* Max PLL phy config */ > {CALIBRATION_CTRL_REG, 0x800, 0x1000, {0x1000, 0x1000, 0x1000, 0x1000}, > ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] arm: mvebu: a38x: Adjust UTMI PHY parameters 2020-06-25 0:48 [PATCH 0/2] arm: mvebu: a38x: USB2 serdes changes Chris Packham 2020-06-25 0:48 ` [PATCH 1/2] arm: mvebu: a38x: Fix typo Chris Packham @ 2020-06-25 0:48 ` Chris Packham 2020-06-29 12:09 ` Stefan Roese 1 sibling, 1 reply; 5+ messages in thread From: Chris Packham @ 2020-06-25 0:48 UTC (permalink / raw) To: u-boot When running USB compliance tests on our Armada-385 hardware platforms we have seen some eye mask violations. Marvell's internal documentation says: Based on silicon test results, it is recommended to change the impedance calibration threshold setting to 0x6 prior to calibration. Port changes from Marvell's u-boot fork[1] to address this. [1] - https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/a6221551 Signed-off-by: Chris Packham <judge.packham@gmail.com> --- .../serdes/a38x/high_speed_env_spec.c | 25 ++++++++++++++++--- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index d4480622c89c..2454730e6d86 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -672,12 +672,29 @@ struct op_params usb2_power_up_params[] = { {0xc200c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0}, /* Phy0 register 3 - TX Channel control 0 */ {0xc400c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0}, - /* check PLLCAL_DONE is set and IMPCAL_DONE is set */ + /* Decrease the amplitude of the low speed eye to meet the spec */ + {0xc000c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0}, + {0xc200c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0}, + {0xc400c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0}, + /* Change the High speed impedance threshold */ + {0xc0008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0}, + {0xc2008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0}, + {0xc4008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0}, + /* Change the squelch level of the receiver to meet the receiver electrical measurements (squelch and receiver sensitivity tests) */ + {0xc0014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0}, + {0xc2014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0}, + {0xc4014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0}, + /* Check PLLCAL_DONE is set and IMPCAL_DONE is set */ {0xc0008, 0x0 /*NA*/, 0x80800000, {0x80800000}, 1, 1000}, - /* check REG_SQCAL_DONE is set */ + /* Check REG_SQCAL_DONE is set */ {0xc0018, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000}, - /* check PLL_READY is set */ - {0xc0000, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000} + /* Check PLL_READY is set */ + {0xc0000, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000}, + /* Start calibrate of high seed impedance */ + {0xc0008, 0x0 /*NA*/, 0x2000, {0x2000}, 0, 0}, + {0x0, 0x0 /*NA*/, 0x0, {0x0}, 10, 0}, + /* De-assert the calibration signal */ + {0xc0008, 0x0 /*NA*/, 0x2000, {0x0}, 0, 0}, }; /* -- 2.27.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] arm: mvebu: a38x: Adjust UTMI PHY parameters 2020-06-25 0:48 ` [PATCH 2/2] arm: mvebu: a38x: Adjust UTMI PHY parameters Chris Packham @ 2020-06-29 12:09 ` Stefan Roese 0 siblings, 0 replies; 5+ messages in thread From: Stefan Roese @ 2020-06-29 12:09 UTC (permalink / raw) To: u-boot On 25.06.20 02:48, Chris Packham wrote: > When running USB compliance tests on our Armada-385 hardware platforms > we have seen some eye mask violations. Marvell's internal documentation > says: Based on silicon test results, it is recommended to change the > impedance calibration threshold setting to 0x6 prior to calibration. > > Port changes from Marvell's u-boot fork[1] to address this. > > [1] - https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/a6221551 > > Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Thanks, Stefan > --- > > .../serdes/a38x/high_speed_env_spec.c | 25 ++++++++++++++++--- > 1 file changed, 21 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c > index d4480622c89c..2454730e6d86 100644 > --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c > +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c > @@ -672,12 +672,29 @@ struct op_params usb2_power_up_params[] = { > {0xc200c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0}, > /* Phy0 register 3 - TX Channel control 0 */ > {0xc400c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0}, > - /* check PLLCAL_DONE is set and IMPCAL_DONE is set */ > + /* Decrease the amplitude of the low speed eye to meet the spec */ > + {0xc000c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0}, > + {0xc200c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0}, > + {0xc400c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0}, > + /* Change the High speed impedance threshold */ > + {0xc0008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0}, > + {0xc2008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0}, > + {0xc4008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0}, > + /* Change the squelch level of the receiver to meet the receiver electrical measurements (squelch and receiver sensitivity tests) */ > + {0xc0014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0}, > + {0xc2014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0}, > + {0xc4014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0}, > + /* Check PLLCAL_DONE is set and IMPCAL_DONE is set */ > {0xc0008, 0x0 /*NA*/, 0x80800000, {0x80800000}, 1, 1000}, > - /* check REG_SQCAL_DONE is set */ > + /* Check REG_SQCAL_DONE is set */ > {0xc0018, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000}, > - /* check PLL_READY is set */ > - {0xc0000, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000} > + /* Check PLL_READY is set */ > + {0xc0000, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000}, > + /* Start calibrate of high seed impedance */ > + {0xc0008, 0x0 /*NA*/, 0x2000, {0x2000}, 0, 0}, > + {0x0, 0x0 /*NA*/, 0x0, {0x0}, 10, 0}, > + /* De-assert the calibration signal */ > + {0xc0008, 0x0 /*NA*/, 0x2000, {0x0}, 0, 0}, > }; > > /* > Viele Gr??e, Stefan -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr at denx.de ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-06-29 12:09 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-06-25 0:48 [PATCH 0/2] arm: mvebu: a38x: USB2 serdes changes Chris Packham 2020-06-25 0:48 ` [PATCH 1/2] arm: mvebu: a38x: Fix typo Chris Packham 2020-06-29 12:09 ` Stefan Roese 2020-06-25 0:48 ` [PATCH 2/2] arm: mvebu: a38x: Adjust UTMI PHY parameters Chris Packham 2020-06-29 12:09 ` Stefan Roese
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