* [PATCH 1/3] rockchip: px30: sync the main rk3326 dtsi from mainline
@ 2020-07-01 9:28 Heiko Stuebner
2020-07-01 9:28 ` [PATCH 2/3] rockchip: px30: sync Odroid Go Advance devicetree from Linux Heiko Stuebner
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Heiko Stuebner @ 2020-07-01 9:28 UTC (permalink / raw)
To: u-boot
From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
The rk3326 is just a trimmed down px30 from a software perspective,
so the mainline rk3326 dtsi also ist just a tiny addition.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
arch/arm/dts/rk3326.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
create mode 100644 arch/arm/dts/rk3326.dtsi
diff --git a/arch/arm/dts/rk3326.dtsi b/arch/arm/dts/rk3326.dtsi
new file mode 100644
index 0000000000..2ba6da1251
--- /dev/null
+++ b/arch/arm/dts/rk3326.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+#include "px30.dtsi"
+
+&display_subsystem {
+ ports = <&vopb_out>;
+};
+
+/delete-node/ &dsi_in_vopl;
+/delete-node/ &lvds_vopl_in;
+/delete-node/ &vopl;
+/delete-node/ &vopl_mmu;
--
2.26.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/3] rockchip: px30: sync Odroid Go Advance devicetree from Linux
2020-07-01 9:28 [PATCH 1/3] rockchip: px30: sync the main rk3326 dtsi from mainline Heiko Stuebner
@ 2020-07-01 9:28 ` Heiko Stuebner
2020-07-08 10:02 ` Kever Yang
2020-07-01 9:28 ` [PATCH 3/3] rockchip: board: add Hardkernel Odroid Go2 board Heiko Stuebner
2020-07-08 10:02 ` [PATCH 1/3] rockchip: px30: sync the main rk3326 dtsi from mainline Kever Yang
2 siblings, 1 reply; 6+ messages in thread
From: Heiko Stuebner @ 2020-07-01 9:28 UTC (permalink / raw)
To: u-boot
From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Get the devicetree from mainline Linux and include it for U-Boot uses.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/rk3326-odroid-go2.dts | 716 +++++++++++++++++++++++++++++
2 files changed, 718 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/rk3326-odroid-go2.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index db7859cd6c..f274c1232a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -71,7 +71,8 @@ dtb-$(CONFIG_MACH_S700) += \
dtb-$(CONFIG_ROCKCHIP_PX30) += \
px30-evb.dtb \
- px30-firefly.dtb
+ px30-firefly.dtb \
+ rk3326-odroid-go2.dtb
dtb-$(CONFIG_ROCKCHIP_RK3036) += \
rk3036-sdk.dtb
diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts
new file mode 100644
index 0000000000..8cd4688c49
--- /dev/null
+++ b/arch/arm/dts/rk3326-odroid-go2.dts
@@ -0,0 +1,716 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Hardkernel Co., Ltd
+ * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3326.dtsi"
+
+/ {
+ model = "ODROID-GO Advance";
+ compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ power-supply = <&vcc_bl>;
+ pwms = <&pwm1 0 25000 0>;
+ };
+
+ adc-joystick {
+ compatible = "adc-joystick";
+ io-channels = <&saradc 1>,
+ <&saradc 2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ axis at 0 {
+ reg = <0>;
+ abs-range = <172 772>;
+ abs-fuzz = <10>;
+ abs-flat = <10>;
+ linux,code = <ABS_X>;
+ };
+
+ axis at 1 {
+ reg = <1>;
+ abs-range = <278 815>;
+ abs-fuzz = <10>;
+ abs-flat = <10>;
+ linux,code = <ABS_Y>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&btn_pins>;
+
+ /*
+ * *** ODROIDGO2-Advance Switch layout ***
+ * |------------------------------------------------|
+ * | sw15 sw16 |
+ * |------------------------------------------------|
+ * | sw1 |-------------------| sw8 |
+ * | sw3 sw4 | | sw7 sw5 |
+ * | sw2 | LCD Display | sw6 |
+ * | | | |
+ * | |-------------------| |
+ * | sw9 sw10 sw11 sw12 sw13 sw14 |
+ * |------------------------------------------------|
+ */
+
+ sw1 {
+ gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
+ label = "DPAD-UP";
+ linux,code = <BTN_DPAD_UP>;
+ };
+ sw2 {
+ gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>;
+ label = "DPAD-DOWN";
+ linux,code = <BTN_DPAD_DOWN>;
+ };
+ sw3 {
+ gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
+ label = "DPAD-LEFT";
+ linux,code = <BTN_DPAD_LEFT>;
+ };
+ sw4 {
+ gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>;
+ label = "DPAD-RIGHT";
+ linux,code = <BTN_DPAD_RIGHT>;
+ };
+ sw5 {
+ gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>;
+ label = "BTN-A";
+ linux,code = <BTN_EAST>;
+ };
+ sw6 {
+ gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "BTN-B";
+ linux,code = <BTN_SOUTH>;
+ };
+ sw7 {
+ gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>;
+ label = "BTN-Y";
+ linux,code = <BTN_WEST>;
+ };
+ sw8 {
+ gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
+ label = "BTN-X";
+ linux,code = <BTN_NORTH>;
+ };
+ sw9 {
+ gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
+ label = "F1";
+ linux,code = <BTN_TRIGGER_HAPPY1>;
+ };
+ sw10 {
+ gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>;
+ label = "F2";
+ linux,code = <BTN_TRIGGER_HAPPY2>;
+ };
+ sw11 {
+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
+ label = "F3";
+ linux,code = <BTN_TRIGGER_HAPPY3>;
+ };
+ sw12 {
+ gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>;
+ label = "F4";
+ linux,code = <BTN_TRIGGER_HAPPY4>;
+ };
+ sw13 {
+ gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>;
+ label = "F5";
+ linux,code = <BTN_TRIGGER_HAPPY5>;
+ };
+ sw14 {
+ gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "F6";
+ linux,code = <BTN_TRIGGER_HAPPY6>;
+ };
+ sw15 {
+ gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
+ label = "TOP-LEFT";
+ linux,code = <BTN_TL>;
+ };
+ sw16 {
+ gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
+ label = "TOP-RIGHT";
+ linux,code = <BTN_TR>;
+ };
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blue_led_pin>;
+
+ blue_led: led-0 {
+ label = "blue:heartbeat";
+ gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ rk817-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "rockchip,rk817-codec";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "MIC_IN", "Mic Jack",
+ "Headphone Jack", "HPOL",
+ "Headphone Jack", "HPOR";
+ simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>;
+ simple-audio-card,codec-hp-det = <1>;
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_2ch>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&rk817_codec>;
+ };
+ };
+
+ vccsys: vccsys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v8_sys";
+ regulator-always-on;
+ regulator-min-microvolt = <3800000>;
+ regulator-max-microvolt = <3800000>;
+ };
+
+ vcc_host: vcc_host {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ vin-supply = <&vccsys>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cru {
+ assigned-clocks = <&cru PLL_NPLL>,
+ <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
+ <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
+ <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>,
+ <&cru PLL_CPLL>;
+
+ assigned-clock-rates = <1188000000>,
+ <200000000>, <200000000>,
+ <150000000>, <150000000>,
+ <100000000>, <200000000>,
+ <17000000>;
+};
+
+&display_subsystem {
+ status = "okay";
+};
+
+&dsi {
+ status = "okay";
+
+ ports {
+ mipi_out: port at 1 {
+ reg = <1>;
+
+ mipi_out_panel: endpoint {
+ remote-endpoint = <&mipi_in_panel>;
+ };
+ };
+ };
+
+ panel at 0 {
+ compatible = "elida,kd35t133";
+ reg = <0>;
+ backlight = <&backlight>;
+ iovcc-supply = <&vcc_lcd>;
+ reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&vcc_lcd>;
+
+ port {
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
+ };
+ };
+};
+
+&dsi_dphy {
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_logic>;
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ i2c-scl-falling-time-ns = <16>;
+ i2c-scl-rising-time-ns = <280>;
+ status = "okay";
+
+ rk817: pmic at 20 {
+ compatible = "rockchip,rk817";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default", "pmic-sleep",
+ "pmic-power-off", "pmic-reset";
+ pinctrl-0 = <&pmic_int>;
+ pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
+ pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
+ pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+ clock-output-names = "rk808-clkout1", "xin32k";
+
+ vcc1-supply = <&vccsys>;
+ vcc2-supply = <&vccsys>;
+ vcc3-supply = <&vccsys>;
+ vcc4-supply = <&vccsys>;
+ vcc5-supply = <&vccsys>;
+ vcc6-supply = <&vccsys>;
+ vcc7-supply = <&vccsys>;
+
+ pinctrl_rk8xx: pinctrl_rk8xx {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rk817_ts_gpio1: rk817_ts_gpio1 {
+ pins = "gpio_ts";
+ function = "pin_fun1";
+ /* output-low; */
+ /* input-enable; */
+ };
+
+ rk817_gt_gpio2: rk817_gt_gpio2 {
+ pins = "gpio_gt";
+ function = "pin_fun1";
+ };
+
+ rk817_pin_ts: rk817_pin_ts {
+ pins = "gpio_ts";
+ function = "pin_fun0";
+ };
+
+ rk817_pin_gt: rk817_pin_gt {
+ pins = "gpio_gt";
+ function = "pin_fun0";
+ };
+
+ rk817_slppin_null: rk817_slppin_null {
+ pins = "gpio_slp";
+ function = "pin_fun0";
+ };
+
+ rk817_slppin_slp: rk817_slppin_slp {
+ pins = "gpio_slp";
+ function = "pin_fun1";
+ };
+
+ rk817_slppin_pwrdn: rk817_slppin_pwrdn {
+ pins = "gpio_slp";
+ function = "pin_fun2";
+ };
+
+ rk817_slppin_rst: rk817_slppin_rst {
+ pins = "gpio_slp";
+ function = "pin_fun3";
+ };
+ };
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <6001>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_3v3: DCDC_REG4 {
+ regulator-name = "vcc_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_1v8: LDO_REG2 {
+ regulator-name = "vcc_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_1v0: LDO_REG3 {
+ regulator-name = "vdd_1v0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG4 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_sd: LDO_REG6 {
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_bl: LDO_REG7 {
+ regulator-name = "vcc_bl";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_lcd: LDO_REG8 {
+ regulator-name = "vcc_lcd";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <2800000>;
+ };
+ };
+
+ vcc_cam: LDO_REG9 {
+ regulator-name = "vcc_cam";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+ };
+
+ battery {
+ compatible = "rk817,battery";
+ ocv_table = <3500 3625 3685 3697 3718 3735 3748
+ 3760 3774 3788 3802 3816 3834 3853
+ 3877 3908 3946 3975 4018 4071 4106>;
+
+ /* KPL605475 Battery Spec */
+ /*
+ Capacity : 3.7V 3000mA
+ Normal Voltage = 3.7V
+ Cut-Off Voltage : 3.1V
+ Internal Impedance : 180 mOhm
+ Charging Voltage : 4.2V
+ Charging Voltage Max : 4.25V
+ Sample resister : 10 mohm
+ */
+ design_capacity = <3000>;
+ design_qmax = <3000>;
+ bat_res = <180>;
+ sleep_enter_current = <300>;
+ sleep_exit_current = <300>;
+ sleep_filter_current = <100>;
+ power_off_thresd = <3500>;
+ zero_algorithm_vol = <3700>;
+ max_soc_offset = <60>;
+ monitor_sec = <5>;
+ virtual_power = <0>;
+ sample_res = <10>;
+ };
+
+ charger {
+ compatible = "rk817,charger";
+ min_input_voltage = <4500>;
+ max_input_current = <1500>;
+ max_chrg_current = <2000>;
+ max_chrg_voltage = <4200>;
+ chrg_term_mode = <0>;
+ chrg_finish_cur = <300>;
+ virtual_power = <0>;
+ sample_res = <10>;
+
+ /* P.C.B rev0.2 DC Detect & Charger Status LED GPIO */
+ dc_det_gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+ chg_led_gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
+
+ extcon = <&u2phy>;
+ };
+
+ rk817_codec: codec {
+ #sound-dai-cells = <0>;
+ compatible = "rockchip,rk817-codec";
+ clocks = <&cru SCLK_I2S1_OUT>;
+ clock-names = "mclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1_2ch_mclk>;
+ hp-volume = <20>;
+ spk-volume = <3>;
+ status = "okay";
+ };
+ };
+};
+
+/* EXT Header(P2): 7(SCL:GPIO0.C2), 8(SDA:GPIO0.C3) */
+&i2c1 {
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+/* I2S 1 Channel Used */
+&i2s1_2ch {
+ status = "okay";
+};
+
+&io_domains {
+ vccio1-supply = <&vcc_3v3>;
+ vccio2-supply = <&vccio_sd>;
+ vccio3-supply = <&vcc_3v3>;
+ vccio4-supply = <&vcc_3v3>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&u2phy {
+ status = "okay";
+
+ u2phy_host: host-port {
+ status = "okay";
+ };
+
+ u2phy_otg: otg-port {
+ status = "disabled";
+ };
+};
+
+&usb20_otg {
+ status = "okay";
+};
+
+/* EXT Header(P2): 2(RXD:GPIO1.C0),3(TXD:.C1),4(CTS:.C2),5(RTS:.C3) */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer &uart1_cts>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m1_xfer>;
+ status = "okay";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&pinctrl {
+ btns {
+ btn_pins: btn-pins {
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ headphone {
+ hp_det: hp-det {
+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ leds {
+ blue_led_pin: blue-led-pin {
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ dc_det: dc-det {
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pmic_int: pmic-int {
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ soc_slppin_gpio: soc_slppin_gpio {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
+ };
+
+ soc_slppin_rst: soc_slppin_rst {
+ rockchip,pins = <0 RK_PA4 2 &pcfg_pull_none>;
+ };
+
+ soc_slppin_slp: soc_slppin_slp {
+ rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
+ };
+ };
+};
--
2.26.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/3] rockchip: board: add Hardkernel Odroid Go2 board
2020-07-01 9:28 [PATCH 1/3] rockchip: px30: sync the main rk3326 dtsi from mainline Heiko Stuebner
2020-07-01 9:28 ` [PATCH 2/3] rockchip: px30: sync Odroid Go Advance devicetree from Linux Heiko Stuebner
@ 2020-07-01 9:28 ` Heiko Stuebner
2020-07-08 10:03 ` Kever Yang
2020-07-08 10:02 ` [PATCH 1/3] rockchip: px30: sync the main rk3326 dtsi from mainline Kever Yang
2 siblings, 1 reply; 6+ messages in thread
From: Heiko Stuebner @ 2020-07-01 9:28 UTC (permalink / raw)
To: u-boot
From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Also known as Odroid Go Advance but named Go2 internally by the
vendor it seems.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 72 +++++++++++++
arch/arm/mach-rockchip/px30/Kconfig | 4 +
board/hardkernel/odroid_go2/Kconfig | 15 +++
board/hardkernel/odroid_go2/MAINTAINERS | 6 ++
board/hardkernel/odroid_go2/Makefile | 7 ++
board/hardkernel/odroid_go2/go2.c | 4 +
configs/odroid-go2_defconfig | 119 +++++++++++++++++++++
include/configs/odroid_go2.h | 17 +++
8 files changed, 244 insertions(+)
create mode 100644 arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
create mode 100644 board/hardkernel/odroid_go2/Kconfig
create mode 100644 board/hardkernel/odroid_go2/MAINTAINERS
create mode 100644 board/hardkernel/odroid_go2/Makefile
create mode 100644 board/hardkernel/odroid_go2/go2.c
create mode 100644 configs/odroid-go2_defconfig
create mode 100644 include/configs/odroid_go2.h
diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
new file mode 100644
index 0000000000..34c9e62025
--- /dev/null
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
+ */
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = &sdmmc;
+ };
+};
+
+&cru {
+ u-boot,dm-pre-reloc;
+};
+
+&dmc {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio0 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio1 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio2 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio3 {
+ u-boot,dm-pre-reloc;
+};
+
+&grf {
+ u-boot,dm-pre-reloc;
+};
+
+&pmucru {
+ u-boot,dm-pre-reloc;
+};
+
+&pmugrf {
+ u-boot,dm-pre-reloc;
+};
+
+&saradc {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+
+ /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
+ u-boot,spl-fifo-mode;
+};
+
+&uart1 {
+ clock-frequency = <24000000>;
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ clock-frequency = <24000000>;
+ u-boot,dm-pre-reloc;
+};
+
+&xin24m {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig
index 9f3ad4f623..f5373c6f9f 100644
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -3,6 +3,9 @@ if ROCKCHIP_PX30
config TARGET_EVB_PX30
bool "EVB_PX30"
+config TARGET_ODROID_GO2
+ bool "ODROID_GO2"
+
config ROCKCHIP_BOOT_MODE_REG
default 0xff010200
@@ -36,6 +39,7 @@ config DEBUG_UART_CHANNEL
For using the UART for early debugging the route to use needs
to be declared (0 or 1).
+source "board/hardkernel/odroid_go2/Kconfig"
source "board/rockchip/evb_px30/Kconfig"
endif
diff --git a/board/hardkernel/odroid_go2/Kconfig b/board/hardkernel/odroid_go2/Kconfig
new file mode 100644
index 0000000000..cf3f7c91d9
--- /dev/null
+++ b/board/hardkernel/odroid_go2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ODROID_GO2
+
+config SYS_BOARD
+ default "odroid_go2"
+
+config SYS_VENDOR
+ default "hardkernel"
+
+config SYS_CONFIG_NAME
+ default "odroid_go2"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/board/hardkernel/odroid_go2/MAINTAINERS b/board/hardkernel/odroid_go2/MAINTAINERS
new file mode 100644
index 0000000000..eab622a70b
--- /dev/null
+++ b/board/hardkernel/odroid_go2/MAINTAINERS
@@ -0,0 +1,6 @@
+GO2
+M: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
+S: Maintained
+F: board/odroid/go2
+F: include/configs/odroid_go2.h
+F: configs/odroid-go2_defconfig
diff --git a/board/hardkernel/odroid_go2/Makefile b/board/hardkernel/odroid_go2/Makefile
new file mode 100644
index 0000000000..51b9d24cfb
--- /dev/null
+++ b/board/hardkernel/odroid_go2/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += go2.o
diff --git a/board/hardkernel/odroid_go2/go2.c b/board/hardkernel/odroid_go2/go2.c
new file mode 100644
index 0000000000..29464ae63e
--- /dev/null
+++ b/board/hardkernel/odroid_go2/go2.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
new file mode 100644
index 0000000000..6eb85a97f7
--- /dev/null
+++ b/configs/odroid-go2_defconfig
@@ -0,0 +1,119 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x4000
+CONFIG_ROCKCHIP_PX30=y
+CONFIG_TARGET_ODROID_GO2=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0xFF160000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_CHANNEL=1
+CONFIG_SPL_TEXT_BASE=0x00000000
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_BEST_MATCH=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_DEFAULT_FDT_FILE="rk3326-odroidgo2.dtb"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
+# CONFIG_TPL_BANNER_PRINT is not set
+CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_ATF=y
+# CONFIG_TPL_FRAMEWORK is not set
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_ITEST is not set
+CONFIG_CMD_SETEXPR=y
+# CONFIG_CMD_MISC is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3326-odroid-go2"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_BUF_SIZE=0x04000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_OTP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_ROCKCHIP_SDRAM_COMMON=y
+CONFIG_DM_RESET=y
+# CONFIG_SPECIFY_CONSOLE_INDEX is not set
+# CONFIG_TPL_DM_SERIAL is not set
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SOUND=y
+CONFIG_SYSRESET=y
+CONFIG_OPTEE=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_LCD=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_LZ4=y
+CONFIG_LZO=y
+CONFIG_ERRNO_STR=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/odroid_go2.h b/include/configs/odroid_go2.h
new file mode 100644
index 0000000000..00eac2d2a8
--- /dev/null
+++ b/include/configs/odroid_go2.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __EVB_PX30_H
+#define __EVB_PX30_H
+
+#include <configs/px30_common.h>
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#endif
--
2.26.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 1/3] rockchip: px30: sync the main rk3326 dtsi from mainline
2020-07-01 9:28 [PATCH 1/3] rockchip: px30: sync the main rk3326 dtsi from mainline Heiko Stuebner
2020-07-01 9:28 ` [PATCH 2/3] rockchip: px30: sync Odroid Go Advance devicetree from Linux Heiko Stuebner
2020-07-01 9:28 ` [PATCH 3/3] rockchip: board: add Hardkernel Odroid Go2 board Heiko Stuebner
@ 2020-07-08 10:02 ` Kever Yang
2 siblings, 0 replies; 6+ messages in thread
From: Kever Yang @ 2020-07-08 10:02 UTC (permalink / raw)
To: u-boot
On 2020/7/1 ??5:28, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
>
> The rk3326 is just a trimmed down px30 from a software perspective,
> so the mainline rk3326 dtsi also ist just a tiny addition.
>
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/dts/rk3326.dtsi | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
> create mode 100644 arch/arm/dts/rk3326.dtsi
>
> diff --git a/arch/arm/dts/rk3326.dtsi b/arch/arm/dts/rk3326.dtsi
> new file mode 100644
> index 0000000000..2ba6da1251
> --- /dev/null
> +++ b/arch/arm/dts/rk3326.dtsi
> @@ -0,0 +1,15 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
> + */
> +
> +#include "px30.dtsi"
> +
> +&display_subsystem {
> + ports = <&vopb_out>;
> +};
> +
> +/delete-node/ &dsi_in_vopl;
> +/delete-node/ &lvds_vopl_in;
> +/delete-node/ &vopl;
> +/delete-node/ &vopl_mmu;
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/3] rockchip: px30: sync Odroid Go Advance devicetree from Linux
2020-07-01 9:28 ` [PATCH 2/3] rockchip: px30: sync Odroid Go Advance devicetree from Linux Heiko Stuebner
@ 2020-07-08 10:02 ` Kever Yang
0 siblings, 0 replies; 6+ messages in thread
From: Kever Yang @ 2020-07-08 10:02 UTC (permalink / raw)
To: u-boot
On 2020/7/1 ??5:28, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
>
> Get the devicetree from mainline Linux and include it for U-Boot uses.
>
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/dts/Makefile | 3 +-
> arch/arm/dts/rk3326-odroid-go2.dts | 716 +++++++++++++++++++++++++++++
> 2 files changed, 718 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/rk3326-odroid-go2.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index db7859cd6c..f274c1232a 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -71,7 +71,8 @@ dtb-$(CONFIG_MACH_S700) += \
>
> dtb-$(CONFIG_ROCKCHIP_PX30) += \
> px30-evb.dtb \
> - px30-firefly.dtb
> + px30-firefly.dtb \
> + rk3326-odroid-go2.dtb
>
> dtb-$(CONFIG_ROCKCHIP_RK3036) += \
> rk3036-sdk.dtb
> diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts
> new file mode 100644
> index 0000000000..8cd4688c49
> --- /dev/null
> +++ b/arch/arm/dts/rk3326-odroid-go2.dts
> @@ -0,0 +1,716 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2019 Hardkernel Co., Ltd
> + * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
> + */
> +
> +/dts-v1/;
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/pinctrl/rockchip.h>
> +#include "rk3326.dtsi"
> +
> +/ {
> + model = "ODROID-GO Advance";
> + compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326";
> +
> + chosen {
> + stdout-path = "serial2:115200n8";
> + };
> +
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + power-supply = <&vcc_bl>;
> + pwms = <&pwm1 0 25000 0>;
> + };
> +
> + adc-joystick {
> + compatible = "adc-joystick";
> + io-channels = <&saradc 1>,
> + <&saradc 2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + axis at 0 {
> + reg = <0>;
> + abs-range = <172 772>;
> + abs-fuzz = <10>;
> + abs-flat = <10>;
> + linux,code = <ABS_X>;
> + };
> +
> + axis at 1 {
> + reg = <1>;
> + abs-range = <278 815>;
> + abs-fuzz = <10>;
> + abs-flat = <10>;
> + linux,code = <ABS_Y>;
> + };
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + pinctrl-names = "default";
> + pinctrl-0 = <&btn_pins>;
> +
> + /*
> + * *** ODROIDGO2-Advance Switch layout ***
> + * |------------------------------------------------|
> + * | sw15 sw16 |
> + * |------------------------------------------------|
> + * | sw1 |-------------------| sw8 |
> + * | sw3 sw4 | | sw7 sw5 |
> + * | sw2 | LCD Display | sw6 |
> + * | | | |
> + * | |-------------------| |
> + * | sw9 sw10 sw11 sw12 sw13 sw14 |
> + * |------------------------------------------------|
> + */
> +
> + sw1 {
> + gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
> + label = "DPAD-UP";
> + linux,code = <BTN_DPAD_UP>;
> + };
> + sw2 {
> + gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>;
> + label = "DPAD-DOWN";
> + linux,code = <BTN_DPAD_DOWN>;
> + };
> + sw3 {
> + gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
> + label = "DPAD-LEFT";
> + linux,code = <BTN_DPAD_LEFT>;
> + };
> + sw4 {
> + gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>;
> + label = "DPAD-RIGHT";
> + linux,code = <BTN_DPAD_RIGHT>;
> + };
> + sw5 {
> + gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>;
> + label = "BTN-A";
> + linux,code = <BTN_EAST>;
> + };
> + sw6 {
> + gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>;
> + label = "BTN-B";
> + linux,code = <BTN_SOUTH>;
> + };
> + sw7 {
> + gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>;
> + label = "BTN-Y";
> + linux,code = <BTN_WEST>;
> + };
> + sw8 {
> + gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
> + label = "BTN-X";
> + linux,code = <BTN_NORTH>;
> + };
> + sw9 {
> + gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
> + label = "F1";
> + linux,code = <BTN_TRIGGER_HAPPY1>;
> + };
> + sw10 {
> + gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>;
> + label = "F2";
> + linux,code = <BTN_TRIGGER_HAPPY2>;
> + };
> + sw11 {
> + gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
> + label = "F3";
> + linux,code = <BTN_TRIGGER_HAPPY3>;
> + };
> + sw12 {
> + gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>;
> + label = "F4";
> + linux,code = <BTN_TRIGGER_HAPPY4>;
> + };
> + sw13 {
> + gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>;
> + label = "F5";
> + linux,code = <BTN_TRIGGER_HAPPY5>;
> + };
> + sw14 {
> + gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>;
> + label = "F6";
> + linux,code = <BTN_TRIGGER_HAPPY6>;
> + };
> + sw15 {
> + gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
> + label = "TOP-LEFT";
> + linux,code = <BTN_TL>;
> + };
> + sw16 {
> + gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
> + label = "TOP-RIGHT";
> + linux,code = <BTN_TR>;
> + };
> + };
> +
> + leds: gpio-leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <&blue_led_pin>;
> +
> + blue_led: led-0 {
> + label = "blue:heartbeat";
> + gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "heartbeat";
> + };
> + };
> +
> + rk817-sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,name = "rockchip,rk817-codec";
> + simple-audio-card,mclk-fs = <256>;
> + simple-audio-card,widgets =
> + "Microphone", "Mic Jack",
> + "Headphone", "Headphone Jack";
> + simple-audio-card,routing =
> + "MIC_IN", "Mic Jack",
> + "Headphone Jack", "HPOL",
> + "Headphone Jack", "HPOR";
> + simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>;
> + simple-audio-card,codec-hp-det = <1>;
> +
> + simple-audio-card,cpu {
> + sound-dai = <&i2s1_2ch>;
> + };
> +
> + simple-audio-card,codec {
> + sound-dai = <&rk817_codec>;
> + };
> + };
> +
> + vccsys: vccsys {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc3v8_sys";
> + regulator-always-on;
> + regulator-min-microvolt = <3800000>;
> + regulator-max-microvolt = <3800000>;
> + };
> +
> + vcc_host: vcc_host {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc_host";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> +
> + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + regulator-always-on;
> + vin-supply = <&vccsys>;
> + };
> +};
> +
> +&cpu0 {
> + cpu-supply = <&vdd_arm>;
> +};
> +
> +&cpu1 {
> + cpu-supply = <&vdd_arm>;
> +};
> +
> +&cpu2 {
> + cpu-supply = <&vdd_arm>;
> +};
> +
> +&cpu3 {
> + cpu-supply = <&vdd_arm>;
> +};
> +
> +&cru {
> + assigned-clocks = <&cru PLL_NPLL>,
> + <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
> + <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
> + <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>,
> + <&cru PLL_CPLL>;
> +
> + assigned-clock-rates = <1188000000>,
> + <200000000>, <200000000>,
> + <150000000>, <150000000>,
> + <100000000>, <200000000>,
> + <17000000>;
> +};
> +
> +&display_subsystem {
> + status = "okay";
> +};
> +
> +&dsi {
> + status = "okay";
> +
> + ports {
> + mipi_out: port at 1 {
> + reg = <1>;
> +
> + mipi_out_panel: endpoint {
> + remote-endpoint = <&mipi_in_panel>;
> + };
> + };
> + };
> +
> + panel at 0 {
> + compatible = "elida,kd35t133";
> + reg = <0>;
> + backlight = <&backlight>;
> + iovcc-supply = <&vcc_lcd>;
> + reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
> + vdd-supply = <&vcc_lcd>;
> +
> + port {
> + mipi_in_panel: endpoint {
> + remote-endpoint = <&mipi_out_panel>;
> + };
> + };
> + };
> +};
> +
> +&dsi_dphy {
> + status = "okay";
> +};
> +
> +&gpu {
> + mali-supply = <&vdd_logic>;
> + status = "okay";
> +};
> +
> +&i2c0 {
> + clock-frequency = <400000>;
> + i2c-scl-falling-time-ns = <16>;
> + i2c-scl-rising-time-ns = <280>;
> + status = "okay";
> +
> + rk817: pmic at 20 {
> + compatible = "rockchip,rk817";
> + reg = <0x20>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
> + pinctrl-names = "default", "pmic-sleep",
> + "pmic-power-off", "pmic-reset";
> + pinctrl-0 = <&pmic_int>;
> + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
> + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
> + pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
> + rockchip,system-power-controller;
> + wakeup-source;
> + #clock-cells = <1>;
> + clock-output-names = "rk808-clkout1", "xin32k";
> +
> + vcc1-supply = <&vccsys>;
> + vcc2-supply = <&vccsys>;
> + vcc3-supply = <&vccsys>;
> + vcc4-supply = <&vccsys>;
> + vcc5-supply = <&vccsys>;
> + vcc6-supply = <&vccsys>;
> + vcc7-supply = <&vccsys>;
> +
> + pinctrl_rk8xx: pinctrl_rk8xx {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + rk817_ts_gpio1: rk817_ts_gpio1 {
> + pins = "gpio_ts";
> + function = "pin_fun1";
> + /* output-low; */
> + /* input-enable; */
> + };
> +
> + rk817_gt_gpio2: rk817_gt_gpio2 {
> + pins = "gpio_gt";
> + function = "pin_fun1";
> + };
> +
> + rk817_pin_ts: rk817_pin_ts {
> + pins = "gpio_ts";
> + function = "pin_fun0";
> + };
> +
> + rk817_pin_gt: rk817_pin_gt {
> + pins = "gpio_gt";
> + function = "pin_fun0";
> + };
> +
> + rk817_slppin_null: rk817_slppin_null {
> + pins = "gpio_slp";
> + function = "pin_fun0";
> + };
> +
> + rk817_slppin_slp: rk817_slppin_slp {
> + pins = "gpio_slp";
> + function = "pin_fun1";
> + };
> +
> + rk817_slppin_pwrdn: rk817_slppin_pwrdn {
> + pins = "gpio_slp";
> + function = "pin_fun2";
> + };
> +
> + rk817_slppin_rst: rk817_slppin_rst {
> + pins = "gpio_slp";
> + function = "pin_fun3";
> + };
> + };
> +
> + regulators {
> + vdd_logic: DCDC_REG1 {
> + regulator-name = "vdd_logic";
> + regulator-min-microvolt = <950000>;
> + regulator-max-microvolt = <1150000>;
> + regulator-ramp-delay = <6001>;
> + regulator-always-on;
> + regulator-boot-on;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <950000>;
> + };
> + };
> +
> + vdd_arm: DCDC_REG2 {
> + regulator-name = "vdd_arm";
> + regulator-min-microvolt = <950000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-ramp-delay = <6001>;
> + regulator-always-on;
> + regulator-boot-on;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + regulator-suspend-microvolt = <950000>;
> + };
> + };
> +
> + vcc_ddr: DCDC_REG3 {
> + regulator-name = "vcc_ddr";
> + regulator-always-on;
> + regulator-boot-on;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + };
> + };
> +
> + vcc_3v3: DCDC_REG4 {
> + regulator-name = "vcc_3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + regulator-suspend-microvolt = <3300000>;
> + };
> + };
> +
> + vcc_1v8: LDO_REG2 {
> + regulator-name = "vcc_1v8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-boot-on;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <1800000>;
> + };
> + };
> +
> + vdd_1v0: LDO_REG3 {
> + regulator-name = "vdd_1v0";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + regulator-boot-on;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <1000000>;
> + };
> + };
> +
> + vcc3v3_pmu: LDO_REG4 {
> + regulator-name = "vcc3v3_pmu";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <3300000>;
> + };
> + };
> +
> + vccio_sd: LDO_REG5 {
> + regulator-name = "vccio_sd";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <3300000>;
> + };
> + };
> +
> + vcc_sd: LDO_REG6 {
> + regulator-name = "vcc_sd";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <3300000>;
> + };
> + };
> +
> + vcc_bl: LDO_REG7 {
> + regulator-name = "vcc_bl";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + regulator-suspend-microvolt = <3300000>;
> + };
> + };
> +
> + vcc_lcd: LDO_REG8 {
> + regulator-name = "vcc_lcd";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + regulator-suspend-microvolt = <2800000>;
> + };
> + };
> +
> + vcc_cam: LDO_REG9 {
> + regulator-name = "vcc_cam";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + regulator-suspend-microvolt = <3000000>;
> + };
> + };
> + };
> +
> + battery {
> + compatible = "rk817,battery";
> + ocv_table = <3500 3625 3685 3697 3718 3735 3748
> + 3760 3774 3788 3802 3816 3834 3853
> + 3877 3908 3946 3975 4018 4071 4106>;
> +
> + /* KPL605475 Battery Spec */
> + /*
> + Capacity : 3.7V 3000mA
> + Normal Voltage = 3.7V
> + Cut-Off Voltage : 3.1V
> + Internal Impedance : 180 mOhm
> + Charging Voltage : 4.2V
> + Charging Voltage Max : 4.25V
> + Sample resister : 10 mohm
> + */
> + design_capacity = <3000>;
> + design_qmax = <3000>;
> + bat_res = <180>;
> + sleep_enter_current = <300>;
> + sleep_exit_current = <300>;
> + sleep_filter_current = <100>;
> + power_off_thresd = <3500>;
> + zero_algorithm_vol = <3700>;
> + max_soc_offset = <60>;
> + monitor_sec = <5>;
> + virtual_power = <0>;
> + sample_res = <10>;
> + };
> +
> + charger {
> + compatible = "rk817,charger";
> + min_input_voltage = <4500>;
> + max_input_current = <1500>;
> + max_chrg_current = <2000>;
> + max_chrg_voltage = <4200>;
> + chrg_term_mode = <0>;
> + chrg_finish_cur = <300>;
> + virtual_power = <0>;
> + sample_res = <10>;
> +
> + /* P.C.B rev0.2 DC Detect & Charger Status LED GPIO */
> + dc_det_gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
> + chg_led_gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
> +
> + extcon = <&u2phy>;
> + };
> +
> + rk817_codec: codec {
> + #sound-dai-cells = <0>;
> + compatible = "rockchip,rk817-codec";
> + clocks = <&cru SCLK_I2S1_OUT>;
> + clock-names = "mclk";
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2s1_2ch_mclk>;
> + hp-volume = <20>;
> + spk-volume = <3>;
> + status = "okay";
> + };
> + };
> +};
> +
> +/* EXT Header(P2): 7(SCL:GPIO0.C2), 8(SDA:GPIO0.C3) */
> +&i2c1 {
> + clock-frequency = <400000>;
> + status = "okay";
> +};
> +
> +/* I2S 1 Channel Used */
> +&i2s1_2ch {
> + status = "okay";
> +};
> +
> +&io_domains {
> + vccio1-supply = <&vcc_3v3>;
> + vccio2-supply = <&vccio_sd>;
> + vccio3-supply = <&vcc_3v3>;
> + vccio4-supply = <&vcc_3v3>;
> + vccio5-supply = <&vcc_3v3>;
> + vccio6-supply = <&vcc_3v3>;
> + status = "okay";
> +};
> +
> +&pmu_io_domains {
> + pmuio1-supply = <&vcc3v3_pmu>;
> + pmuio2-supply = <&vcc3v3_pmu>;
> + status = "okay";
> +};
> +
> +&pwm1 {
> + status = "okay";
> +};
> +
> +&saradc {
> + vref-supply = <&vcc_1v8>;
> + status = "okay";
> +};
> +
> +&sdmmc {
> + bus-width = <4>;
> + cap-sd-highspeed;
> + card-detect-delay = <200>;
> + cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/
> + sd-uhs-sdr12;
> + sd-uhs-sdr25;
> + sd-uhs-sdr50;
> + sd-uhs-sdr104;
> + vmmc-supply = <&vcc_sd>;
> + vqmmc-supply = <&vccio_sd>;
> + status = "okay";
> +};
> +
> +&tsadc {
> + status = "okay";
> +};
> +
> +&u2phy {
> + status = "okay";
> +
> + u2phy_host: host-port {
> + status = "okay";
> + };
> +
> + u2phy_otg: otg-port {
> + status = "disabled";
> + };
> +};
> +
> +&usb20_otg {
> + status = "okay";
> +};
> +
> +/* EXT Header(P2): 2(RXD:GPIO1.C0),3(TXD:.C1),4(CTS:.C2),5(RTS:.C3) */
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_xfer &uart1_cts>;
> + status = "okay";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart2m1_xfer>;
> + status = "okay";
> +};
> +
> +&vopb {
> + status = "okay";
> +};
> +
> +&vopb_mmu {
> + status = "okay";
> +};
> +
> +&pinctrl {
> + btns {
> + btn_pins: btn-pins {
> + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
> + <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
> + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
> + <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
> + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
> + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
> + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
> + <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
> + <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
> + <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
> + <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
> + <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
> + <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
> + <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
> + <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
> + <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
> + };
> + };
> +
> + headphone {
> + hp_det: hp-det {
> + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
> + };
> + };
> +
> + leds {
> + blue_led_pin: blue-led-pin {
> + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + pmic {
> + dc_det: dc-det {
> + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> +
> + pmic_int: pmic-int {
> + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
> + };
> +
> + soc_slppin_gpio: soc_slppin_gpio {
> + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
> + };
> +
> + soc_slppin_rst: soc_slppin_rst {
> + rockchip,pins = <0 RK_PA4 2 &pcfg_pull_none>;
> + };
> +
> + soc_slppin_slp: soc_slppin_slp {
> + rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
> + };
> + };
> +};
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/3] rockchip: board: add Hardkernel Odroid Go2 board
2020-07-01 9:28 ` [PATCH 3/3] rockchip: board: add Hardkernel Odroid Go2 board Heiko Stuebner
@ 2020-07-08 10:03 ` Kever Yang
0 siblings, 0 replies; 6+ messages in thread
From: Kever Yang @ 2020-07-08 10:03 UTC (permalink / raw)
To: u-boot
On 2020/7/1 ??5:28, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
>
> Also known as Odroid Go Advance but named Go2 internally by the
> vendor it seems.
>
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 72 +++++++++++++
> arch/arm/mach-rockchip/px30/Kconfig | 4 +
> board/hardkernel/odroid_go2/Kconfig | 15 +++
> board/hardkernel/odroid_go2/MAINTAINERS | 6 ++
> board/hardkernel/odroid_go2/Makefile | 7 ++
> board/hardkernel/odroid_go2/go2.c | 4 +
> configs/odroid-go2_defconfig | 119 +++++++++++++++++++++
> include/configs/odroid_go2.h | 17 +++
> 8 files changed, 244 insertions(+)
> create mode 100644 arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> create mode 100644 board/hardkernel/odroid_go2/Kconfig
> create mode 100644 board/hardkernel/odroid_go2/MAINTAINERS
> create mode 100644 board/hardkernel/odroid_go2/Makefile
> create mode 100644 board/hardkernel/odroid_go2/go2.c
> create mode 100644 configs/odroid-go2_defconfig
> create mode 100644 include/configs/odroid_go2.h
>
> diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> new file mode 100644
> index 0000000000..34c9e62025
> --- /dev/null
> +++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> @@ -0,0 +1,72 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
> + */
> +
> +/ {
> + chosen {
> + u-boot,spl-boot-order = &sdmmc;
> + };
> +};
> +
> +&cru {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&dmc {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&gpio0 {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&gpio1 {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&gpio2 {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&gpio3 {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&grf {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&pmucru {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&pmugrf {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&saradc {
> + u-boot,dm-pre-reloc;
> + status = "okay";
> +};
> +
> +&sdmmc {
> + u-boot,dm-pre-reloc;
> +
> + /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
> + u-boot,spl-fifo-mode;
> +};
> +
> +&uart1 {
> + clock-frequency = <24000000>;
> + u-boot,dm-pre-reloc;
> +};
> +
> +&uart2 {
> + clock-frequency = <24000000>;
> + u-boot,dm-pre-reloc;
> +};
> +
> +&xin24m {
> + u-boot,dm-pre-reloc;
> +};
> diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig
> index 9f3ad4f623..f5373c6f9f 100644
> --- a/arch/arm/mach-rockchip/px30/Kconfig
> +++ b/arch/arm/mach-rockchip/px30/Kconfig
> @@ -3,6 +3,9 @@ if ROCKCHIP_PX30
> config TARGET_EVB_PX30
> bool "EVB_PX30"
>
> +config TARGET_ODROID_GO2
> + bool "ODROID_GO2"
> +
> config ROCKCHIP_BOOT_MODE_REG
> default 0xff010200
>
> @@ -36,6 +39,7 @@ config DEBUG_UART_CHANNEL
> For using the UART for early debugging the route to use needs
> to be declared (0 or 1).
>
> +source "board/hardkernel/odroid_go2/Kconfig"
> source "board/rockchip/evb_px30/Kconfig"
>
> endif
> diff --git a/board/hardkernel/odroid_go2/Kconfig b/board/hardkernel/odroid_go2/Kconfig
> new file mode 100644
> index 0000000000..cf3f7c91d9
> --- /dev/null
> +++ b/board/hardkernel/odroid_go2/Kconfig
> @@ -0,0 +1,15 @@
> +if TARGET_ODROID_GO2
> +
> +config SYS_BOARD
> + default "odroid_go2"
> +
> +config SYS_VENDOR
> + default "hardkernel"
> +
> +config SYS_CONFIG_NAME
> + default "odroid_go2"
> +
> +config BOARD_SPECIFIC_OPTIONS # dummy
> + def_bool y
> +
> +endif
> diff --git a/board/hardkernel/odroid_go2/MAINTAINERS b/board/hardkernel/odroid_go2/MAINTAINERS
> new file mode 100644
> index 0000000000..eab622a70b
> --- /dev/null
> +++ b/board/hardkernel/odroid_go2/MAINTAINERS
> @@ -0,0 +1,6 @@
> +GO2
> +M: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> +S: Maintained
> +F: board/odroid/go2
> +F: include/configs/odroid_go2.h
> +F: configs/odroid-go2_defconfig
> diff --git a/board/hardkernel/odroid_go2/Makefile b/board/hardkernel/odroid_go2/Makefile
> new file mode 100644
> index 0000000000..51b9d24cfb
> --- /dev/null
> +++ b/board/hardkernel/odroid_go2/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y += go2.o
> diff --git a/board/hardkernel/odroid_go2/go2.c b/board/hardkernel/odroid_go2/go2.c
> new file mode 100644
> index 0000000000..29464ae63e
> --- /dev/null
> +++ b/board/hardkernel/odroid_go2/go2.c
> @@ -0,0 +1,4 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2019 Rockchip Electronics Co., Ltd
> + */
> diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
> new file mode 100644
> index 0000000000..6eb85a97f7
> --- /dev/null
> +++ b/configs/odroid-go2_defconfig
> @@ -0,0 +1,119 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_SYS_TEXT_BASE=0x00200000
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_ENV_SIZE=0x4000
> +CONFIG_ENV_OFFSET=0x4000
> +CONFIG_ROCKCHIP_PX30=y
> +CONFIG_TARGET_ODROID_GO2=y
> +CONFIG_TPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
> +CONFIG_SPL_STACK_R_ADDR=0x600000
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_DEBUG_UART_BASE=0xFF160000
> +CONFIG_DEBUG_UART_CLOCK=24000000
> +CONFIG_DEBUG_UART=y
> +CONFIG_DEBUG_UART_CHANNEL=1
> +CONFIG_SPL_TEXT_BASE=0x00000000
> +CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
> +# CONFIG_ANDROID_BOOT_IMAGE is not set
> +CONFIG_FIT=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_FIT_BEST_MATCH=y
> +CONFIG_SPL_LOAD_FIT=y
> +# CONFIG_CONSOLE_MUX is not set
> +CONFIG_DEFAULT_FDT_FILE="rk3326-odroidgo2.dtb"
> +CONFIG_MISC_INIT_R=y
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_DISPLAY_BOARDINFO_LATE=y
> +CONFIG_SPL_BOOTROM_SUPPORT=y
> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> +CONFIG_SPL_STACK_R=y
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
> +# CONFIG_TPL_BANNER_PRINT is not set
> +CONFIG_SPL_CRC32_SUPPORT=y
> +CONFIG_SPL_ATF=y
> +# CONFIG_TPL_FRAMEWORK is not set
> +CONFIG_SPL_I2C_SUPPORT=y
> +CONFIG_SPL_POWER_SUPPORT=y
> +# CONFIG_CMD_BOOTD is not set
> +# CONFIG_CMD_ELF is not set
> +# CONFIG_CMD_IMI is not set
> +# CONFIG_CMD_XIMG is not set
> +# CONFIG_CMD_LZMADEC is not set
> +# CONFIG_CMD_UNZIP is not set
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_GPT=y
> +# CONFIG_CMD_LOADB is not set
> +# CONFIG_CMD_LOADS is not set
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_USB_MASS_STORAGE=y
> +# CONFIG_CMD_ITEST is not set
> +CONFIG_CMD_SETEXPR=y
> +# CONFIG_CMD_MISC is not set
> +# CONFIG_SPL_DOS_PARTITION is not set
> +# CONFIG_ISO_PARTITION is not set
> +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_OF_LIVE=y
> +CONFIG_DEFAULT_DEVICE_TREE="rk3326-odroid-go2"
> +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_REGMAP=y
> +CONFIG_SPL_REGMAP=y
> +CONFIG_SYSCON=y
> +CONFIG_SPL_SYSCON=y
> +CONFIG_CLK=y
> +CONFIG_SPL_CLK=y
> +CONFIG_FASTBOOT_BUF_ADDR=0x800800
> +CONFIG_FASTBOOT_BUF_SIZE=0x04000000
> +CONFIG_FASTBOOT_FLASH=y
> +CONFIG_FASTBOOT_FLASH_MMC_DEV=0
> +CONFIG_ROCKCHIP_GPIO=y
> +CONFIG_SYS_I2C_ROCKCHIP=y
> +CONFIG_MISC=y
> +CONFIG_ROCKCHIP_OTP=y
> +CONFIG_MMC_DW=y
> +CONFIG_MMC_DW_ROCKCHIP=y
> +CONFIG_PHY_REALTEK=y
> +CONFIG_DM_ETH=y
> +CONFIG_ETH_DESIGNWARE=y
> +CONFIG_GMAC_ROCKCHIP=y
> +CONFIG_PINCTRL=y
> +CONFIG_SPL_PINCTRL=y
> +CONFIG_DM_PMIC=y
> +CONFIG_PMIC_RK8XX=y
> +CONFIG_REGULATOR_PWM=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_REGULATOR_RK8XX=y
> +CONFIG_PWM_ROCKCHIP=y
> +CONFIG_RAM=y
> +CONFIG_SPL_RAM=y
> +CONFIG_TPL_RAM=y
> +CONFIG_ROCKCHIP_SDRAM_COMMON=y
> +CONFIG_DM_RESET=y
> +# CONFIG_SPECIFY_CONSOLE_INDEX is not set
> +# CONFIG_TPL_DM_SERIAL is not set
> +CONFIG_DEBUG_UART_SHIFT=2
> +CONFIG_DEBUG_UART_SKIP_INIT=y
> +CONFIG_SOUND=y
> +CONFIG_SYSRESET=y
> +CONFIG_OPTEE=y
> +CONFIG_DM_THERMAL=y
> +CONFIG_USB=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_EHCI_GENERIC=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GADGET_DWC2_OTG=y
> +CONFIG_DM_VIDEO=y
> +CONFIG_DISPLAY=y
> +CONFIG_LCD=y
> +CONFIG_SPL_TINY_MEMSET=y
> +CONFIG_TPL_TINY_MEMSET=y
> +CONFIG_LZ4=y
> +CONFIG_LZO=y
> +CONFIG_ERRNO_STR=y
> +# CONFIG_EFI_LOADER is not set
> diff --git a/include/configs/odroid_go2.h b/include/configs/odroid_go2.h
> new file mode 100644
> index 0000000000..00eac2d2a8
> --- /dev/null
> +++ b/include/configs/odroid_go2.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd
> + */
> +
> +#ifndef __EVB_PX30_H
> +#define __EVB_PX30_H
> +
> +#include <configs/px30_common.h>
> +
> +#define CONFIG_SYS_MMC_ENV_DEV 0
> +
> +#define ROCKCHIP_DEVICE_SETTINGS \
> + "stdout=serial,vidconsole\0" \
> + "stderr=serial,vidconsole\0"
> +
> +#endif
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-07-08 10:03 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-07-01 9:28 [PATCH 1/3] rockchip: px30: sync the main rk3326 dtsi from mainline Heiko Stuebner
2020-07-01 9:28 ` [PATCH 2/3] rockchip: px30: sync Odroid Go Advance devicetree from Linux Heiko Stuebner
2020-07-08 10:02 ` Kever Yang
2020-07-01 9:28 ` [PATCH 3/3] rockchip: board: add Hardkernel Odroid Go2 board Heiko Stuebner
2020-07-08 10:03 ` Kever Yang
2020-07-08 10:02 ` [PATCH 1/3] rockchip: px30: sync the main rk3326 dtsi from mainline Kever Yang
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