PINE64 Rock64 - How to get SPI driver working

PINE64 Rock64 - How to get SPI driver working

[Johannes Krottmayer]

Hello,

I just compiled U-Boot v2020.04 for a PINE64 Rock media board.
It compiles fine without errors, but when I try to probe the
on board flash I get an error:

=> sf probe
Invalid bus 0 (err=-19)
Failed to initialize SPI flash at 0:0 (error -19)
=>

SPI is activated in the Device-Tree blob. I also added support
to the Rockchip SPI driver (added IDS strings for this SoC).

In the device config I added the following:

CONFIG_SPI=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SPI_FLASH=y

But the driver still doesn't work. Output of DM (shortened):

=> dm tree
[...]
  spi           0  [   ]   rockchip_spi          |-- spi at ff190000

  spi_flash     0  [   ]   spi_flash_std         |   `-- spiflash at 0
[...]

What is missing? Is there a way to load driver?

Any kind of help is highly appreciated.

-- 
Kind regards,

Johannes K.

PINE64 Rock64 - How to get SPI driver working

[Kamal R. Prasad]

Hello,

 I want to add a helper function to uboot i.e
uboot# help
will show a list of commands. I want to add 1 for my own private command.
which file contains the list of cmd that will be displayed and the
indirection?
thanks
-kamal


On Wed, May 20, 2020 at 8:58 AM Johannes Krottmayer <krjdev@gmail.com>
wrote:

> Hello,
>
> I just compiled U-Boot v2020.04 for a PINE64 Rock media board.
> It compiles fine without errors, but when I try to probe the
> on board flash I get an error:
>
> => sf probe
> Invalid bus 0 (err=-19)
> Failed to initialize SPI flash at 0:0 (error -19)
> =>
>
> SPI is activated in the Device-Tree blob. I also added support
> to the Rockchip SPI driver (added IDS strings for this SoC).
>
> In the device config I added the following:
>
> CONFIG_SPI=y
> CONFIG_ROCKCHIP_SPI=y
> CONFIG_SPI_FLASH=y
>
> But the driver still doesn't work. Output of DM (shortened):
>
> => dm tree
> [...]
>   spi           0  [   ]   rockchip_spi          |-- spi at ff190000
>
>   spi_flash     0  [   ]   spi_flash_std         |   `-- spiflash at 0
> [...]
>
> What is missing? Is there a way to load driver?
>
> Any kind of help is highly appreciated.
>
> --
> Kind regards,
>
> Johannes K.
>

PINE64 Rock64 - How to get SPI driver working

[Kever Yang]

Jagan may some idea here.


I would suggest you to add some log in the spi/flash driver for bind, 
probe and etc

to check what's wrong.


Thanks,

- Kever

On 2020/5/20 ??7:41, Johannes Krottmayer wrote:
> Hello,
>
> I just compiled U-Boot v2020.04 for a PINE64 Rock media board.
> It compiles fine without errors, but when I try to probe the
> on board flash I get an error:
>
> => sf probe
> Invalid bus 0 (err=-19)
> Failed to initialize SPI flash at 0:0 (error -19)
> =>
>
> SPI is activated in the Device-Tree blob. I also added support
> to the Rockchip SPI driver (added IDS strings for this SoC).
>
> In the device config I added the following:
>
> CONFIG_SPI=y
> CONFIG_ROCKCHIP_SPI=y
> CONFIG_SPI_FLASH=y
>
> But the driver still doesn't work. Output of DM (shortened):
>
> => dm tree
> [...]
>    spi           0  [   ]   rockchip_spi          |-- spi at ff190000
>
>    spi_flash     0  [   ]   spi_flash_std         |   `-- spiflash at 0
> [...]
>
> What is missing? Is there a way to load driver?
>
> Any kind of help is highly appreciated.
>

PINE64 Rock64 - How to get SPI driver working

[Johannes Krottmayer]

Hi Kever,

I think you answered the wrong person. :)

Okay, thanks for the suggestions.

I will check the sources. There was also a missing alias
in the Device-Tree source. I have added the specific alias
for the SPI bus. Now I'm getting the error code -2.

I'm new with U-Boot and the source code itself, but I
think the problem occurs still in the device tree file for
the specific board.

Cheers,

Johannes K.


On 21.05.20 at 15:35,  Kever Yang wrote:
> Jagan may some idea here.
> 
> 
> I would suggest you to add some log in the spi/flash driver for bind, 
> probe and etc
> 
> to check what's wrong.
> 
> 
> Thanks,
> 
> - Kever
> 
> On 2020/5/20 ??7:41, Johannes Krottmayer wrote:
>> Hello,
>>
>> I just compiled U-Boot v2020.04 for a PINE64 Rock media board.
>> It compiles fine without errors, but when I try to probe the
>> on board flash I get an error:
>>
>> => sf probe
>> Invalid bus 0 (err=-19)
>> Failed to initialize SPI flash at 0:0 (error -19)
>> =>
>>
>> SPI is activated in the Device-Tree blob. I also added support
>> to the Rockchip SPI driver (added IDS strings for this SoC).
>>
>> In the device config I added the following:
>>
>> CONFIG_SPI=y
>> CONFIG_ROCKCHIP_SPI=y
>> CONFIG_SPI_FLASH=y
>>
>> But the driver still doesn't work. Output of DM (shortened):
>>
>> => dm tree
>> [...]
>>    spi           0  [   ]   rockchip_spi          |-- spi at ff190000
>>
>>    spi_flash     0  [   ]   spi_flash_std         |   `-- spiflash at 0
>> [...]
>>
>> What is missing? Is there a way to load driver?
>>
>> Any kind of help is highly appreciated.
>>
> 
> 

PINE64 Rock64 - How to get SPI driver working

[Peter Robinson]

On Fri, May 22, 2020 at 12:12 AM Johannes Krottmayer <krjdev@gmail.com> wrote:
>
> Hi Kever,
>
> I think you answered the wrong person. :)
>
> Okay, thanks for the suggestions.
>
> I will check the sources. There was also a missing alias
> in the Device-Tree source. I have added the specific alias
> for the SPI bus. Now I'm getting the error code -2.

Make sure you enable the driver for the actual flash chip too, some of
the popular ones are:
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_GIGADEVICE=y

> I'm new with U-Boot and the source code itself, but I
> think the problem occurs still in the device tree file for
> the specific board.
>
> Cheers,
>
> Johannes K.
>
>
> On 21.05.20 at 15:35,  Kever Yang wrote:
> > Jagan may some idea here.
> >
> >
> > I would suggest you to add some log in the spi/flash driver for bind,
> > probe and etc
> >
> > to check what's wrong.
> >
> >
> > Thanks,
> >
> > - Kever
> >
> > On 2020/5/20 ??7:41, Johannes Krottmayer wrote:
> >> Hello,
> >>
> >> I just compiled U-Boot v2020.04 for a PINE64 Rock media board.
> >> It compiles fine without errors, but when I try to probe the
> >> on board flash I get an error:
> >>
> >> => sf probe
> >> Invalid bus 0 (err=-19)
> >> Failed to initialize SPI flash at 0:0 (error -19)
> >> =>
> >>
> >> SPI is activated in the Device-Tree blob. I also added support
> >> to the Rockchip SPI driver (added IDS strings for this SoC).
> >>
> >> In the device config I added the following:
> >>
> >> CONFIG_SPI=y
> >> CONFIG_ROCKCHIP_SPI=y
> >> CONFIG_SPI_FLASH=y
> >>
> >> But the driver still doesn't work. Output of DM (shortened):
> >>
> >> => dm tree
> >> [...]
> >>    spi           0  [   ]   rockchip_spi          |-- spi at ff190000
> >>
> >>    spi_flash     0  [   ]   spi_flash_std         |   `-- spiflash at 0
> >> [...]
> >>
> >> What is missing? Is there a way to load driver?
> >>
> >> Any kind of help is highly appreciated.
> >>
> >
> >

PINE64 Rock64 - How to get SPI driver working

[Johannes Krottmayer]

Sorry for my late response.

Thanks for the suggestions.

On 22.05.20 at 16:28,  Peter Robinson wrote:
> Make sure you enable the driver for the actual flash chip too, some of
> the popular ones are:
> CONFIG_SPI_FLASH_WINBOND=y
> CONFIG_SPI_FLASH_MACRONIX=y
> CONFIG_SPI_FLASH_SPANSION=y
> CONFIG_SPI_FLASH_GIGADEVICE=y

I have enabled 'CONFIG_SPI_FLASH_GIGADEVICE'. But still getting
the same error code (-2). On board is the GD25Q127C from Gigadevice.

The device ID for the operation code 0x9F according to the datasheet
should be 0xC84018. I also found this device ID in the SPI-NOR IDS
file.

PINE64 Rock64 - How to get SPI driver working

[Johannes Krottmayer]

I finally resolved the issue:

=> sf probe
SF: Detected gd25q128 with page size 256 Bytes, erase size 4 KiB, total
16 MiB
=>

The flash device will be correctly detected.
The problem was missing support in the clock driver of the SoC.

Should I release a patch for it?

On 24.06.20 at 17:52,  Johannes Krottmayer wrote:
> Sorry for my late response.
> 
> Thanks for the suggestions.
> 
> On 22.05.20 at 16:28,  Peter Robinson wrote:
>> Make sure you enable the driver for the actual flash chip too, some of
>> the popular ones are:
>> CONFIG_SPI_FLASH_WINBOND=y
>> CONFIG_SPI_FLASH_MACRONIX=y
>> CONFIG_SPI_FLASH_SPANSION=y
>> CONFIG_SPI_FLASH_GIGADEVICE=y
> 
> I have enabled 'CONFIG_SPI_FLASH_GIGADEVICE'. But still getting
> the same error code (-2). On board is the GD25Q127C from Gigadevice.
> 
> The device ID for the operation code 0x9F according to the datasheet
> should be 0xC84018. I also found this device ID in the SPI-NOR IDS
> file.
> 

[PATCH] rockchip: rk3328: Add SPI support

[Johannes Krottmayer]

Add U-Boot SPI support for the RK3328

Signed-off-by: Johannes Krottmayer <krjdev@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
---

It's a initial SPI support. Not sure if "rk3399_spi_params" is also
needed. Probing of the SPI flash devices works. Tested with the
PINE64 Rock64 board.

Okay?

 arch/arm/dts/rk3328-u-boot.dtsi   |  5 +++++
 drivers/clk/rockchip/clk_rk3328.c | 31 +++++++++++++++++++++++++++++++
 drivers/spi/rk_spi.c              |  2 ++
 3 files changed, 38 insertions(+)

diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
index c69e13e11e..c980daae99 100644
--- a/arch/arm/dts/rk3328-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-u-boot.dtsi
@@ -7,6 +7,7 @@
 	aliases {
 		mmc0 = &emmc;
 		mmc1 = &sdmmc;
+ 		spi0 = &spi0;
 	};
 
 	chosen {
@@ -66,3 +67,7 @@
 &usb20_otg {
 	hnp-srp-disable;
 };
+
+&spi0 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
index 02d3b08efa..bd95ab832b 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -555,6 +555,31 @@ static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz)
 	return rk3328_saradc_get_clk(cru);
 }
 
+static ulong rk3328_spi_get_clk(struct rk3328_cru *cru)
+{
+	u32 div, val;
+
+	val = readl(&cru->clksel_con[24]);
+	div = (val & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT;
+
+	return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rk3328_spi_set_clk(struct rk3328_cru *cru, uint hz)
+{
+	u32 src_clk_div;
+
+	src_clk_div = GPLL_HZ / hz;
+	assert(src_clk_div < 128);
+
+	rk_clrsetreg(&cru->clksel_con[24],
+		     CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
+		     CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
+		     (src_clk_div - 1) << CLK_PWM_DIV_CON_SHIFT);
+
+	return rk3328_spi_get_clk(cru);
+}
+
 static ulong rk3328_clk_get_rate(struct clk *clk)
 {
 	struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
@@ -581,6 +606,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk)
 	case SCLK_SARADC:
 		rate = rk3328_saradc_get_clk(priv->cru);
 		break;
+	case SCLK_SPI:
+		rate = rk3328_spi_get_clk(priv->cru);
+		break;
 	default:
 		return -ENOENT;
 	}
@@ -617,6 +645,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
 	case SCLK_SARADC:
 		ret = rk3328_saradc_set_clk(priv->cru, rate);
 		break;
+    case SCLK_SPI:
+		ret = rk3328_spi_set_clk(priv->cru, rate);
+        break;
 	case DCLK_LCDC:
 	case SCLK_PDM:
 	case SCLK_RTC32K:
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 833cb04922..0495e04945 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -545,7 +545,9 @@ const  struct rockchip_spi_params rk3399_spi_params = {
 };
 
 static const struct udevice_id rockchip_spi_ids[] = {
+	{ .compatible = "rockchip,rk3066-spi" },
 	{ .compatible = "rockchip,rk3288-spi" },
+	{ .compatible = "rockchip,rk3328-spi" },
 	{ .compatible = "rockchip,rk3368-spi",
 	  .data = (ulong)&rk3399_spi_params },
 	{ .compatible = "rockchip,rk3399-spi",
-- 
2.26.2

[PATCH] rockchip: rock64-rk3328: Add SPI Flash support

[Johannes Krottmayer]

Add SPI Flash support for the PINE64 Rock64 board

Signed-off-by: Johannes Krottmayer <krjdev@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
---

Initial SPI Flash support.

Okay?

 arch/arm/dts/rk3328-rock64-u-boot.dtsi | 6 ++++++
 configs/rock64-rk3328_defconfig        | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
index f076075076..7340ef95f1 100644
--- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
@@ -46,3 +46,9 @@
 &vcc_sd {
 	u-boot,dm-spl;
 };
+
+&spi0 {
+	spi_flash: spiflash at 0 {
+		u-boot,dm-pre-reloc;
+	};
+};
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
index f123826358..0a51e51a0c 100644
--- a/configs/rock64-rk3328_defconfig
+++ b/configs/rock64-rk3328_defconfig
@@ -97,3 +97,5 @@ CONFIG_SPL_TINY_MEMSET=y
 CONFIG_TPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
 CONFIG_SMBIOS_MANUFACTURER="pine64"
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
-- 
2.26.2

[PATCH] rockchip: rk3328: Add SPI support

[Kever Yang]

Hi Johannes,

The changes look good to me, but you need to split the patch into 3 patches:

- rk3328 clock driver;

- rkspi driver;

- rk3328-u-boot.dtsi

BTW: the patch no need reply-to previous mail, you can make a new thread.

Thanks,

- Kever

On 2020/7/4 ??2:08, Johannes Krottmayer wrote:
> Add U-Boot SPI support for the RK3328
>
> Signed-off-by: Johannes Krottmayer <krjdev@gmail.com>
> Cc: Kever Yang <kever.yang@rock-chips.com>
> Cc: Jagan Teki <jagan@amarulasolutions.com>
> ---
>
> It's a initial SPI support. Not sure if "rk3399_spi_params" is also
> needed. Probing of the SPI flash devices works. Tested with the
> PINE64 Rock64 board.
>
> Okay?
>
>   arch/arm/dts/rk3328-u-boot.dtsi   |  5 +++++
>   drivers/clk/rockchip/clk_rk3328.c | 31 +++++++++++++++++++++++++++++++
>   drivers/spi/rk_spi.c              |  2 ++
>   3 files changed, 38 insertions(+)
>
> diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
> index c69e13e11e..c980daae99 100644
> --- a/arch/arm/dts/rk3328-u-boot.dtsi
> +++ b/arch/arm/dts/rk3328-u-boot.dtsi
> @@ -7,6 +7,7 @@
>   	aliases {
>   		mmc0 = &emmc;
>   		mmc1 = &sdmmc;
> + 		spi0 = &spi0;
>   	};
>   
>   	chosen {
> @@ -66,3 +67,7 @@
>   &usb20_otg {
>   	hnp-srp-disable;
>   };
> +
> +&spi0 {
> +	u-boot,dm-pre-reloc;
> +};
> diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
> index 02d3b08efa..bd95ab832b 100644
> --- a/drivers/clk/rockchip/clk_rk3328.c
> +++ b/drivers/clk/rockchip/clk_rk3328.c
> @@ -555,6 +555,31 @@ static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz)
>   	return rk3328_saradc_get_clk(cru);
>   }
>   
> +static ulong rk3328_spi_get_clk(struct rk3328_cru *cru)
> +{
> +	u32 div, val;
> +
> +	val = readl(&cru->clksel_con[24]);
> +	div = (val & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT;
> +
> +	return DIV_TO_RATE(OSC_HZ, div);
> +}
> +
> +static ulong rk3328_spi_set_clk(struct rk3328_cru *cru, uint hz)
> +{
> +	u32 src_clk_div;
> +
> +	src_clk_div = GPLL_HZ / hz;
> +	assert(src_clk_div < 128);
> +
> +	rk_clrsetreg(&cru->clksel_con[24],
> +		     CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
> +		     CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
> +		     (src_clk_div - 1) << CLK_PWM_DIV_CON_SHIFT);
> +
> +	return rk3328_spi_get_clk(cru);
> +}
> +
>   static ulong rk3328_clk_get_rate(struct clk *clk)
>   {
>   	struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
> @@ -581,6 +606,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk)
>   	case SCLK_SARADC:
>   		rate = rk3328_saradc_get_clk(priv->cru);
>   		break;
> +	case SCLK_SPI:
> +		rate = rk3328_spi_get_clk(priv->cru);
> +		break;
>   	default:
>   		return -ENOENT;
>   	}
> @@ -617,6 +645,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
>   	case SCLK_SARADC:
>   		ret = rk3328_saradc_set_clk(priv->cru, rate);
>   		break;
> +    case SCLK_SPI:
> +		ret = rk3328_spi_set_clk(priv->cru, rate);
> +        break;
>   	case DCLK_LCDC:
>   	case SCLK_PDM:
>   	case SCLK_RTC32K:
> diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
> index 833cb04922..0495e04945 100644
> --- a/drivers/spi/rk_spi.c
> +++ b/drivers/spi/rk_spi.c
> @@ -545,7 +545,9 @@ const  struct rockchip_spi_params rk3399_spi_params = {
>   };
>   
>   static const struct udevice_id rockchip_spi_ids[] = {
> +	{ .compatible = "rockchip,rk3066-spi" },
>   	{ .compatible = "rockchip,rk3288-spi" },
> +	{ .compatible = "rockchip,rk3328-spi" },
>   	{ .compatible = "rockchip,rk3368-spi",
>   	  .data = (ulong)&rk3399_spi_params },
>   	{ .compatible = "rockchip,rk3399-spi",

[PATCH] rockchip: rk3328: Add SPI support

[Kever Yang]

Hi Johannes,

 ??? Do you have plan to update for this patch?


Thanks,

- Kever

On 2020/7/8 ??6:08, Kever Yang wrote:
> Hi Johannes,
>
> The changes look good to me, but you need to split the patch into 3 
> patches:
>
> - rk3328 clock driver;
>
> - rkspi driver;
>
> - rk3328-u-boot.dtsi
>
> BTW: the patch no need reply-to previous mail, you can make a new thread.
>
> Thanks,
>
> - Kever
>
> On 2020/7/4 ??2:08, Johannes Krottmayer wrote:
>> Add U-Boot SPI support for the RK3328
>>
>> Signed-off-by: Johannes Krottmayer <krjdev@gmail.com>
>> Cc: Kever Yang <kever.yang@rock-chips.com>
>> Cc: Jagan Teki <jagan@amarulasolutions.com>
>> ---
>>
>> It's a initial SPI support. Not sure if "rk3399_spi_params" is also
>> needed. Probing of the SPI flash devices works. Tested with the
>> PINE64 Rock64 board.
>>
>> Okay?
>>
>> ? arch/arm/dts/rk3328-u-boot.dtsi?? |? 5 +++++
>> ? drivers/clk/rockchip/clk_rk3328.c | 31 +++++++++++++++++++++++++++++++
>> ? drivers/spi/rk_spi.c????????????? |? 2 ++
>> ? 3 files changed, 38 insertions(+)
>>
>> diff --git a/arch/arm/dts/rk3328-u-boot.dtsi 
>> b/arch/arm/dts/rk3328-u-boot.dtsi
>> index c69e13e11e..c980daae99 100644
>> --- a/arch/arm/dts/rk3328-u-boot.dtsi
>> +++ b/arch/arm/dts/rk3328-u-boot.dtsi
>> @@ -7,6 +7,7 @@
>> ????? aliases {
>> ????????? mmc0 = &emmc;
>> ????????? mmc1 = &sdmmc;
>> +???????? spi0 = &spi0;
>> ????? };
>> ? ????? chosen {
>> @@ -66,3 +67,7 @@
>> ? &usb20_otg {
>> ????? hnp-srp-disable;
>> ? };
>> +
>> +&spi0 {
>> +??? u-boot,dm-pre-reloc;
>> +};
>> diff --git a/drivers/clk/rockchip/clk_rk3328.c 
>> b/drivers/clk/rockchip/clk_rk3328.c
>> index 02d3b08efa..bd95ab832b 100644
>> --- a/drivers/clk/rockchip/clk_rk3328.c
>> +++ b/drivers/clk/rockchip/clk_rk3328.c
>> @@ -555,6 +555,31 @@ static ulong rk3328_saradc_set_clk(struct 
>> rk3328_cru *cru, uint hz)
>> ????? return rk3328_saradc_get_clk(cru);
>> ? }
>> ? +static ulong rk3328_spi_get_clk(struct rk3328_cru *cru)
>> +{
>> +??? u32 div, val;
>> +
>> +??? val = readl(&cru->clksel_con[24]);
>> +??? div = (val & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT;
>> +
>> +??? return DIV_TO_RATE(OSC_HZ, div);
>> +}
>> +
>> +static ulong rk3328_spi_set_clk(struct rk3328_cru *cru, uint hz)
>> +{
>> +??? u32 src_clk_div;
>> +
>> +??? src_clk_div = GPLL_HZ / hz;
>> +??? assert(src_clk_div < 128);
>> +
>> +??? rk_clrsetreg(&cru->clksel_con[24],
>> +???????????? CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
>> +???????????? CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
>> +???????????? (src_clk_div - 1) << CLK_PWM_DIV_CON_SHIFT);
>> +
>> +??? return rk3328_spi_get_clk(cru);
>> +}
>> +
>> ? static ulong rk3328_clk_get_rate(struct clk *clk)
>> ? {
>> ????? struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
>> @@ -581,6 +606,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk)
>> ????? case SCLK_SARADC:
>> ????????? rate = rk3328_saradc_get_clk(priv->cru);
>> ????????? break;
>> +??? case SCLK_SPI:
>> +??????? rate = rk3328_spi_get_clk(priv->cru);
>> +??????? break;
>> ????? default:
>> ????????? return -ENOENT;
>> ????? }
>> @@ -617,6 +645,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, 
>> ulong rate)
>> ????? case SCLK_SARADC:
>> ????????? ret = rk3328_saradc_set_clk(priv->cru, rate);
>> ????????? break;
>> +??? case SCLK_SPI:
>> +??????? ret = rk3328_spi_set_clk(priv->cru, rate);
>> +??????? break;
>> ????? case DCLK_LCDC:
>> ????? case SCLK_PDM:
>> ????? case SCLK_RTC32K:
>> diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
>> index 833cb04922..0495e04945 100644
>> --- a/drivers/spi/rk_spi.c
>> +++ b/drivers/spi/rk_spi.c
>> @@ -545,7 +545,9 @@ const? struct rockchip_spi_params 
>> rk3399_spi_params = {
>> ? };
>> ? ? static const struct udevice_id rockchip_spi_ids[] = {
>> +??? { .compatible = "rockchip,rk3066-spi" },
>> ????? { .compatible = "rockchip,rk3288-spi" },
>> +??? { .compatible = "rockchip,rk3328-spi" },
>> ????? { .compatible = "rockchip,rk3368-spi",
>> ??????? .data = (ulong)&rk3399_spi_params },
>> ????? { .compatible = "rockchip,rk3399-spi",
>
>

[PATCH] rockchip: rk3328: Add SPI support

[Johannes Krottmayer]

Hi Kever,

On 18.07.20 at 05:02,  Kever Yang wrote:
> Hi Johannes,
> 
>  ??? Do you have plan to update for this patch?

I think this thread is obsolete. You have already applied
the improved two patch (RK3328, PINE64 Rock64) series
later in a new thread.

Many thanks for the apply.

Kind regards,

Johannes K.

> 
> Thanks,
> 
> - Kever
> 
> On 2020/7/8 ??6:08, Kever Yang wrote:
>> Hi Johannes,
>>
>> The changes look good to me, but you need to split the patch into 3 
>> patches:
>>
>> - rk3328 clock driver;
>>
>> - rkspi driver;
>>
>> - rk3328-u-boot.dtsi
>>
>> BTW: the patch no need reply-to previous mail, you can make a new thread.
>>
>> Thanks,
>>
>> - Kever
>>
>> On 2020/7/4 ??2:08, Johannes Krottmayer wrote:
>>> Add U-Boot SPI support for the RK3328
>>>
>>> Signed-off-by: Johannes Krottmayer <krjdev@gmail.com>
>>> Cc: Kever Yang <kever.yang@rock-chips.com>
>>> Cc: Jagan Teki <jagan@amarulasolutions.com>
>>> ---
>>>
>>> It's a initial SPI support. Not sure if "rk3399_spi_params" is also
>>> needed. Probing of the SPI flash devices works. Tested with the
>>> PINE64 Rock64 board.
>>>
>>> Okay?
>>>
>>> ? arch/arm/dts/rk3328-u-boot.dtsi?? |? 5 +++++
>>> ? drivers/clk/rockchip/clk_rk3328.c | 31 +++++++++++++++++++++++++++++++
>>> ? drivers/spi/rk_spi.c????????????? |? 2 ++
>>> ? 3 files changed, 38 insertions(+)
>>>
>>> diff --git a/arch/arm/dts/rk3328-u-boot.dtsi 
>>> b/arch/arm/dts/rk3328-u-boot.dtsi
>>> index c69e13e11e..c980daae99 100644
>>> --- a/arch/arm/dts/rk3328-u-boot.dtsi
>>> +++ b/arch/arm/dts/rk3328-u-boot.dtsi
>>> @@ -7,6 +7,7 @@
>>> ????? aliases {
>>> ????????? mmc0 = &emmc;
>>> ????????? mmc1 = &sdmmc;
>>> +???????? spi0 = &spi0;
>>> ????? };
>>> ? ????? chosen {
>>> @@ -66,3 +67,7 @@
>>> ? &usb20_otg {
>>> ????? hnp-srp-disable;
>>> ? };
>>> +
>>> +&spi0 {
>>> +??? u-boot,dm-pre-reloc;
>>> +};
>>> diff --git a/drivers/clk/rockchip/clk_rk3328.c 
>>> b/drivers/clk/rockchip/clk_rk3328.c
>>> index 02d3b08efa..bd95ab832b 100644
>>> --- a/drivers/clk/rockchip/clk_rk3328.c
>>> +++ b/drivers/clk/rockchip/clk_rk3328.c
>>> @@ -555,6 +555,31 @@ static ulong rk3328_saradc_set_clk(struct 
>>> rk3328_cru *cru, uint hz)
>>> ????? return rk3328_saradc_get_clk(cru);
>>> ? }
>>> ? +static ulong rk3328_spi_get_clk(struct rk3328_cru *cru)
>>> +{
>>> +??? u32 div, val;
>>> +
>>> +??? val = readl(&cru->clksel_con[24]);
>>> +??? div = (val & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT;
>>> +
>>> +??? return DIV_TO_RATE(OSC_HZ, div);
>>> +}
>>> +
>>> +static ulong rk3328_spi_set_clk(struct rk3328_cru *cru, uint hz)
>>> +{
>>> +??? u32 src_clk_div;
>>> +
>>> +??? src_clk_div = GPLL_HZ / hz;
>>> +??? assert(src_clk_div < 128);
>>> +
>>> +??? rk_clrsetreg(&cru->clksel_con[24],
>>> +???????????? CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
>>> +???????????? CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
>>> +???????????? (src_clk_div - 1) << CLK_PWM_DIV_CON_SHIFT);
>>> +
>>> +??? return rk3328_spi_get_clk(cru);
>>> +}
>>> +
>>> ? static ulong rk3328_clk_get_rate(struct clk *clk)
>>> ? {
>>> ????? struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
>>> @@ -581,6 +606,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk)
>>> ????? case SCLK_SARADC:
>>> ????????? rate = rk3328_saradc_get_clk(priv->cru);
>>> ????????? break;
>>> +??? case SCLK_SPI:
>>> +??????? rate = rk3328_spi_get_clk(priv->cru);
>>> +??????? break;
>>> ????? default:
>>> ????????? return -ENOENT;
>>> ????? }
>>> @@ -617,6 +645,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, 
>>> ulong rate)
>>> ????? case SCLK_SARADC:
>>> ????????? ret = rk3328_saradc_set_clk(priv->cru, rate);
>>> ????????? break;
>>> +??? case SCLK_SPI:
>>> +??????? ret = rk3328_spi_set_clk(priv->cru, rate);
>>> +??????? break;
>>> ????? case DCLK_LCDC:
>>> ????? case SCLK_PDM:
>>> ????? case SCLK_RTC32K:
>>> diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
>>> index 833cb04922..0495e04945 100644
>>> --- a/drivers/spi/rk_spi.c
>>> +++ b/drivers/spi/rk_spi.c
>>> @@ -545,7 +545,9 @@ const? struct rockchip_spi_params 
>>> rk3399_spi_params = {
>>> ? };
>>> ? ? static const struct udevice_id rockchip_spi_ids[] = {
>>> +??? { .compatible = "rockchip,rk3066-spi" },
>>> ????? { .compatible = "rockchip,rk3288-spi" },
>>> +??? { .compatible = "rockchip,rk3328-spi" },
>>> ????? { .compatible = "rockchip,rk3368-spi",
>>> ??????? .data = (ulong)&rk3399_spi_params },
>>> ????? { .compatible = "rockchip,rk3399-spi",
>>
>>
> 
>