From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Fri, 10 Jul 2020 16:22:15 -0400 Subject: [PATCH v5 5/6] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit) In-Reply-To: <20200603124345.18595-6-m.szyprowski@samsung.com> References: <20200603124345.18595-1-m.szyprowski@samsung.com> <20200603124345.18595-6-m.szyprowski@samsung.com> Message-ID: <20200710202215.GL6246@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Wed, Jun 03, 2020 at 02:43:44PM +0200, Marek Szyprowski wrote: > Create a non-cacheable mapping for the 0x600000000 physical memory region, > where MMIO registers for the PCIe XHCI controller are instantiated by the > PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM > 32bit mode, this region is mapped at 0xff800000 CPU virtual address. > > Signed-off-by: Marek Szyprowski Applied to u-boot/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 659 bytes Desc: not available URL: