From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andy Shevchenko Date: Tue, 28 Jul 2020 12:56:25 +0300 Subject: [PATCH v1 1/2] x86: sipi_vector: Append appropriate suffixes Message-ID: <20200728095626.28445-1-andriy.shevchenko@linux.intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Assembler is not happy: arch/x86/cpu/sipi_vector.S: Assembler messages: arch/x86/cpu/sipi_vector.S:134: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp' arch/x86/cpu/sipi_vector.S:139: Warning: no instruction mnemonic suffix given and no register operands; using default for `bts' arch/x86/cpu/sipi_vector.S:157: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp' Fix this by adding appropriate suffixes to the assembler commands. Fixes: 45b5a37836d5 ("x86: Add multi-processor init") Signed-off-by: Andy Shevchenko --- arch/x86/cpu/sipi_vector.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/cpu/sipi_vector.S b/arch/x86/cpu/sipi_vector.S index 40cc27f1e1d0..fa1e6cb19af4 100644 --- a/arch/x86/cpu/sipi_vector.S +++ b/arch/x86/cpu/sipi_vector.S @@ -131,12 +131,12 @@ ap_start: jnz microcode_done /* Determine if parallel microcode loading is allowed */ - cmp $0xffffffff, microcode_lock + cmpl $0xffffffff, microcode_lock je load_microcode /* Protect microcode loading */ lock_microcode: - lock bts $0, microcode_lock + lock btsl $0, microcode_lock jc lock_microcode load_microcode: @@ -154,7 +154,7 @@ load_microcode: popa /* Unconditionally unlock microcode loading */ - cmp $0xffffffff, microcode_lock + cmpl $0xffffffff, microcode_lock je microcode_done xor %eax, %eax -- 2.27.0