From: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
To: u-boot@lists.denx.de
Subject: [PATCH 4/6] include/configs: aspeed: Remove hardcoded variables
Date: Mon, 3 Aug 2020 17:36:08 +0800 [thread overview]
Message-ID: <20200803093610.3222-5-chiawei_wang@aspeedtech.com> (raw)
In-Reply-To: <20200803093610.3222-1-chiawei_wang@aspeedtech.com>
The hardcoded platform variables such as DRAM base address are not
common to Aspeed SoCs AST24xx/AST25xx/AST26xx. This patch replaces
those hardcoded with macros defined in a newly added header, where
the basic SoC HW information are assigned accordingly.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
---
arch/arm/include/asm/arch-aspeed/platform.h | 20 ++++++++++++++++++++
include/configs/aspeed-common.h | 16 +++++++++-------
2 files changed, 29 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/include/asm/arch-aspeed/platform.h
diff --git a/arch/arm/include/asm/arch-aspeed/platform.h b/arch/arm/include/asm/arch-aspeed/platform.h
new file mode 100644
index 0000000000..6cee036f54
--- /dev/null
+++ b/arch/arm/include/asm/arch-aspeed/platform.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ * Ryan Chen <ryan_chen@aspeedtech.com>
+ *
+ */
+
+#ifndef _ASM_ARCH_PLATFORM_H
+#define _ASM_ARCH_PLATFORM_H
+
+#if defined(CONFIG_ASPEED_AST2500)
+#define ASPEED_MAC_COUNT 2
+#define ASPEED_DRAM_BASE 0x80000000
+#define ASPEED_SRAM_BASE 0x1e720000
+#define ASPEED_SRAM_SIZE 0x9000
+#else
+#err "Unrecognized Aspeed platform."
+#endif
+
+#endif
diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h
index 1295a6cd19..14dd5c795d 100644
--- a/include/configs/aspeed-common.h
+++ b/include/configs/aspeed-common.h
@@ -7,22 +7,24 @@
* (C) Copyright 2016 Google, Inc
*/
-#ifndef __AST_COMMON_CONFIG_H
-#define __AST_COMMON_CONFIG_H
+#ifndef _ASPEED_COMMON_CONFIG_H
+#define _ASPEED_COMMON_CONFIG_H
+
+#include <asm/arch/platform.h>
/* Misc CPU related */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_SDRAM_BASE ASPEED_DRAM_BASE
#ifdef CONFIG_PRE_CON_BUF_SZ
-#define CONFIG_SYS_INIT_RAM_ADDR (0x1e720000 + CONFIG_PRE_CON_BUF_SZ)
-#define CONFIG_SYS_INIT_RAM_SIZE (36*1024 - CONFIG_PRE_CON_BUF_SZ)
+#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ)
+#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ)
#else
-#define CONFIG_SYS_INIT_RAM_ADDR (0x1e720000)
-#define CONFIG_SYS_INIT_RAM_SIZE (36*1024)
+#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE)
+#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE)
#endif
#define SYS_INIT_RAM_END (CONFIG_SYS_INIT_RAM_ADDR \
--
2.17.1
next prev parent reply other threads:[~2020-08-03 9:36 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-03 9:36 [PATCH 0/6] Refactor Aspeed SoCs support Chia-Wei, Wang
2020-08-03 9:36 ` [PATCH 1/6] MAINTAINERS: Add maintainers for Aspeed SoCs Chia-Wei, Wang
2020-08-14 19:51 ` Tom Rini
2020-08-03 9:36 ` [PATCH 2/6] aspeed: ast2500: Add lowlevel_init assembly Chia-Wei, Wang
2020-08-14 19:51 ` Tom Rini
2020-08-03 9:36 ` [PATCH 3/6] cosmetic: aspeed: ast2500: Rename board file Chia-Wei, Wang
2020-08-14 19:52 ` Tom Rini
2020-08-03 9:36 ` Chia-Wei, Wang [this message]
2020-08-14 19:52 ` [PATCH 4/6] include/configs: aspeed: Remove hardcoded variables Tom Rini
2020-08-03 9:36 ` [PATCH 5/6] configs: evb-ast2500: Move BOOTCOMMAND from header to defconfig Chia-Wei, Wang
2020-08-14 19:52 ` Tom Rini
2020-08-03 9:36 ` [PATCH 6/6] configs: evb-ast2500: Convert to OF_SEPARATE Chia-Wei, Wang
2020-08-14 19:52 ` Tom Rini
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