* [PATCH 1/3] clk: mt7622: add needed clocks for ssusb-node
2020-08-14 7:15 [PATCH 0/3] Add USB for MT7622/MT7623 Frank Wunderlich
@ 2020-08-14 7:15 ` Frank Wunderlich
2020-08-14 7:15 ` [PATCH 2/3] arm: dts: mt7622: add USB nodes Frank Wunderlich
2020-08-14 7:15 ` [PATCH 3/3] arm: dts: mt7623: " Frank Wunderlich
2 siblings, 0 replies; 4+ messages in thread
From: Frank Wunderlich @ 2020-08-14 7:15 UTC (permalink / raw)
To: u-boot
From: Frank Wunderlich <frank-w@public-files.de>
MT7622 needs additional clock definitions to work properly
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
drivers/clk/mediatek/clk-mt7622.c | 42 +++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 95c5232957..85df13338e 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -521,6 +521,20 @@ static const struct mtk_gate_regs sgmii_cg_regs = {
.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
}
+static const struct mtk_gate_regs ssusb_cg_regs = {
+ .set_ofs = 0x30,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x30,
+};
+
+#define GATE_SSUSB(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &ssusb_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+}
+
static const struct mtk_gate sgmii_cgs[] = {
GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2),
GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3),
@@ -528,6 +542,15 @@ static const struct mtk_gate sgmii_cgs[] = {
GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
};
+static const struct mtk_gate ssusb_cgs[] = {
+ GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0),
+ GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1),
+ GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5),
+ GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6),
+ GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_AXI_SEL, 7),
+ GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_HIF_SEL, 8),
+};
+
static const struct mtk_clk_tree mt7622_clk_tree = {
.xtal_rate = 25 * MHZ,
.xtal2_rate = 25 * MHZ,
@@ -631,6 +654,11 @@ static int mt7622_sgmiisys_probe(struct udevice *dev)
return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs);
}
+static int mt7622_ssusbsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, ssusb_cgs);
+}
+
static const struct udevice_id mt7622_apmixed_compat[] = {
{ .compatible = "mediatek,mt7622-apmixedsys" },
{ }
@@ -671,6 +699,11 @@ static const struct udevice_id mt7622_mcucfg_compat[] = {
{ }
};
+static const struct udevice_id mt7622_ssusbsys_compat[] = {
+ { .compatible = "mediatek,mt7622-ssusbsys" },
+ { }
+};
+
U_BOOT_DRIVER(mtk_mcucfg) = {
.name = "mt7622-mcucfg",
.id = UCLASS_SYSCON,
@@ -747,3 +780,12 @@ U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
+
+U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
+ .name = "mt7622-clock-ssusbsys",
+ .id = UCLASS_CLK,
+ .of_match = mt7622_ssusbsys_compat,
+ .probe = mt7622_ssusbsys_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH 2/3] arm: dts: mt7622: add USB nodes
2020-08-14 7:15 [PATCH 0/3] Add USB for MT7622/MT7623 Frank Wunderlich
2020-08-14 7:15 ` [PATCH 1/3] clk: mt7622: add needed clocks for ssusb-node Frank Wunderlich
@ 2020-08-14 7:15 ` Frank Wunderlich
2020-08-14 7:15 ` [PATCH 3/3] arm: dts: mt7623: " Frank Wunderlich
2 siblings, 0 replies; 4+ messages in thread
From: Frank Wunderlich @ 2020-08-14 7:15 UTC (permalink / raw)
To: u-boot
From: Frank Wunderlich <frank-w@public-files.de>
Add DTS nodes for MT7622/BPI-R64
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
this is based on xHCI driver Update (0.96 support) [1] and BPI-R64 DTS [2]
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=195331
[2] https://patchwork.ozlabs.org/project/uboot/list/?series=194922
---
arch/arm/dts/mt7622-bpi-r64.dts | 8 +++++
arch/arm/dts/mt7622.dtsi | 64 +++++++++++++++++++++++++++++++++
2 files changed, 72 insertions(+)
diff --git a/arch/arm/dts/mt7622-bpi-r64.dts b/arch/arm/dts/mt7622-bpi-r64.dts
index aaa4d9a246..7f780db1a5 100644
--- a/arch/arm/dts/mt7622-bpi-r64.dts
+++ b/arch/arm/dts/mt7622-bpi-r64.dts
@@ -244,3 +244,11 @@
output-low;
};
};
+
+&ssusb {
+ status = "okay";
+};
+
+&u3phy {
+ status = "okay";
+};
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
index 2802909671..e94884ad66 100644
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -81,6 +81,12 @@
#clock-cells = <0>;
};
+ clk25m: dummy25m {
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ #clock-cells = <0>;
+ };
+
infracfg: infracfg at 10000000 {
compatible = "mediatek,mt7622-infracfg",
"syscon";
@@ -192,6 +198,14 @@
status = "disabled";
};
+ ssusbsys: ssusbsys at 1a000000 {
+ compatible = "mediatek,mt7622-ssusbsys",
+ "syscon";
+ reg = <0x1a000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
pciesys: pciesys at 1a100800 {
compatible = "mediatek,mt7622-pciesys", "syscon";
reg = <0x1a100800 0x1000>;
@@ -314,6 +328,56 @@
};
};
+ ssusb: usb at 1a0c0000 {
+ compatible = "mediatek,mt7622-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0x1a0c0000 0x01000>,
+ <0x1a0c4700 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
+ clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
+ <&ssusbsys CLK_SSUSB_REF_EN>,
+ <&ssusbsys CLK_SSUSB_MCU_EN>,
+ <&ssusbsys CLK_SSUSB_DMA_EN>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>,
+ <&u2port1 PHY_TYPE_USB2>;
+ status = "disabled";
+ };
+
+ u3phy: usb-phy at 1a0c4000 {
+ compatible = "mediatek,mt7622-u3phy",
+ "mediatek,generic-tphy-v1";
+ reg = <0x1a0c4000 0x700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ u2port0: usb-phy at 1a0c4800 {
+ reg = <0x1a0c4800 0x0100>;
+ #phy-cells = <1>;
+ clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
+ clock-names = "ref";
+ };
+
+ u3port0: usb-phy at 1a0c4900 {
+ reg = <0x1a0c4900 0x0700>;
+ #phy-cells = <1>;
+ clocks = <&clk25m>;
+ clock-names = "ref";
+ };
+
+ u2port1: usb-phy at 1a0c5000 {
+ reg = <0x1a0c5000 0x0100>;
+ #phy-cells = <1>;
+ clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
+ clock-names = "ref";
+ };
+ };
+
ethsys: syscon at 1b000000 {
compatible = "mediatek,mt7622-ethsys", "syscon";
reg = <0x1b000000 0x1000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH 3/3] arm: dts: mt7623: add USB nodes
2020-08-14 7:15 [PATCH 0/3] Add USB for MT7622/MT7623 Frank Wunderlich
2020-08-14 7:15 ` [PATCH 1/3] clk: mt7622: add needed clocks for ssusb-node Frank Wunderlich
2020-08-14 7:15 ` [PATCH 2/3] arm: dts: mt7622: add USB nodes Frank Wunderlich
@ 2020-08-14 7:15 ` Frank Wunderlich
2 siblings, 0 replies; 4+ messages in thread
From: Frank Wunderlich @ 2020-08-14 7:15 UTC (permalink / raw)
To: u-boot
From: Frank Wunderlich <frank-w@public-files.de>
This adds USB nodes for MT7623/BPI-R2
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
needs xHCI 0.96 support [1]
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=195331
---
arch/arm/dts/mt7623.dtsi | 46 ++++++++++++++++++++++++
arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 16 +++++++++
2 files changed, 62 insertions(+)
diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
index 0452889ef8..e753e08545 100644
--- a/arch/arm/dts/mt7623.dtsi
+++ b/arch/arm/dts/mt7623.dtsi
@@ -352,6 +352,52 @@
};
};
+ usb1: usb at 1a1c0000 {
+ compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci";
+ reg = <0x1a1c0000 0x1000>, <0x1a1c4700 0x0100>;
+ reg-names = "mac", "ippc";
+ power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
+ clocks = <&hifsys CLK_HIFSYS_USB0PHY>, <&topckgen CLK_TOP_ETHIF_SEL>;
+ clock-names = "sys_ck", "ref_ck";
+ phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
+ status = "disabled";
+ };
+
+ u3phy1: usb-phy1 at 1a1c4000 {
+ compatible = "mediatek,mt7623-tphy", "mediatek,generic-tphy-v1";
+
+ reg = <0x1a1c4000 0x0700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ u2port0: usb-phy at 1a1c4800 {
+ reg = <0x1a1c4800 0x0100>;
+ #phy-cells = <1>;
+ clocks = <&topckgen CLK_TOP_USB_PHY48M>;
+ clock-names = "ref";
+ };
+
+ u3port0: usb-phy at 1a1c4900 {
+ reg = <0x1a1c4900 0x0700>;
+ #phy-cells = <1>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ };
+ };
+
+ usb2: usb at 1a240000 {
+ compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci";
+ reg = <0x1a240000 0x1000>, <0x1a244700 0x0100>;
+ reg-names = "mac", "ippc";
+ power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
+ clocks = <&hifsys CLK_HIFSYS_USB1PHY>, <&topckgen CLK_TOP_ETHIF_SEL>;
+ clock-names = "sys_ck", "ref_ck";
+ phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
+ status = "disabled";
+ };
+
u3phy2: usb-phy at 1a244000 {
compatible = "mediatek,generic-tphy-v1";
reg = <0x1a244000 0x0700>;
diff --git a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
index bcedcf20f1..ef07369627 100644
--- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
+++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
@@ -248,3 +248,19 @@
pinctrl-0 = <&uart2_pins_a>;
status = "okay";
};
+
+&usb1 {
+ status = "okay";
+};
+
+&u3phy1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+&u3phy2 {
+ status = "okay";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread