[PATCH 2/3] arm: dts: mt7622: add USB nodes

Frank Wunderlich
2020-08-14T07:15:09Z

Add DTS nodes for MT7622/BPI-R64

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
this is based on xHCI driver Update (0.96 support) [1] and BPI-R64 DTS [2]

[1] https://patchwork.ozlabs.org/project/uboot/list/?series=195331
[2] https://patchwork.ozlabs.org/project/uboot/list/?series=194922
---
arch/arm/dts/mt7622-bpi-r64.dts | 8 +++++
arch/arm/dts/mt7622.dtsi | 64 +++++++++++++++++++++++++++++++++
2 files changed, 72 insertions(+)

diff --git a/arch/arm/dts/mt7622-bpi-r64.dts b/arch/arm/dts/mt7622-bpi-r64.dts
index aaa4d9a246..7f780db1a5 100644
--- a/arch/arm/dts/mt7622-bpi-r64.dts
+++ b/arch/arm/dts/mt7622-bpi-r64.dts
@@ -244,3 +244,11 @@
output-low;
};
};
+
+&ssusb {
+ status = "okay";
+};
+
+&u3phy {
+ status = "okay";
+};
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
index 2802909671..e94884ad66 100644
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -81,6 +81,12 @@
#clock-cells = <0>;
};

+ clk25m: dummy25m {
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ #clock-cells = <0>;
+ };
+
infracfg: infracfg at 10000000 {
compatible = "mediatek,mt7622-infracfg",
"syscon";
@@ -192,6 +198,14 @@
status = "disabled";
};

+ ssusbsys: ssusbsys at 1a000000 {
+ compatible = "mediatek,mt7622-ssusbsys",
+ "syscon";
+ reg = <0x1a000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
pciesys: pciesys at 1a100800 {
compatible = "mediatek,mt7622-pciesys", "syscon";
reg = <0x1a100800 0x1000>;
@@ -314,6 +328,56 @@
};
};

+ ssusb: usb at 1a0c0000 {
+ compatible = "mediatek,mt7622-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0x1a0c0000 0x01000>,
+ <0x1a0c4700 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
+ clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
+ <&ssusbsys CLK_SSUSB_REF_EN>,
+ <&ssusbsys CLK_SSUSB_MCU_EN>,
+ <&ssusbsys CLK_SSUSB_DMA_EN>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>,
+ <&u2port1 PHY_TYPE_USB2>;
+ status = "disabled";
+ };
+
+ u3phy: usb-phy at 1a0c4000 {
+ compatible = "mediatek,mt7622-u3phy",
+ "mediatek,generic-tphy-v1";
+ reg = <0x1a0c4000 0x700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ u2port0: usb-phy at 1a0c4800 {
+ reg = <0x1a0c4800 0x0100>;
+ #phy-cells = <1>;
+ clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
+ clock-names = "ref";
+ };
+
+ u3port0: usb-phy at 1a0c4900 {
+ reg = <0x1a0c4900 0x0700>;
+ #phy-cells = <1>;
+ clocks = <&clk25m>;
+ clock-names = "ref";
+ };
+
+ u2port1: usb-phy at 1a0c5000 {
+ reg = <0x1a0c5000 0x0100>;
+ #phy-cells = <1>;
+ clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
+ clock-names = "ref";
+ };
+ };
+
ethsys: syscon at 1b000000 {
compatible = "mediatek,mt7622-ethsys", "syscon";
reg = <0x1b000000 0x1000>;
--
2.25.1