From mboxrd@z Thu Jan 1 00:00:00 1970 From: Frank Wunderlich Date: Wed, 19 Aug 2020 10:02:18 +0200 Subject: [PATCH v2 04/11] reset: add basic reset controller for pciesys In-Reply-To: <20200819080225.4267-1-linux@fw-web.de> References: <20200819080225.4267-1-linux@fw-web.de> Message-ID: <20200819080225.4267-5-linux@fw-web.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Frank Wunderlich bind reset controller to pciesys Signed-off-by: Frank Wunderlich --- drivers/clk/mediatek/clk-mt7622.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index bd86b5b974..d53ed69189 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -594,6 +594,20 @@ static int mt7622_pciesys_probe(struct udevice *dev) return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs); } +static int mt7622_pciesys_bind(struct udevice *dev) +{ + int ret = 0; + + if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) { +// PCIESYS uses in linux also 0x34 = ETHSYS reset controller + ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1); + if (ret) + debug("Warning: failed to bind reset controller\n"); + } + + return ret; +} + static int mt7622_ethsys_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs); @@ -710,6 +724,7 @@ U_BOOT_DRIVER(mtk_clk_pciesys) = { .id = UCLASS_CLK, .of_match = mt7622_pciesys_compat, .probe = mt7622_pciesys_probe, + .bind = mt7622_pciesys_bind, .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, }; -- 2.25.1