From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Thu, 20 Aug 2020 07:35:39 +0200 Subject: [PATCH v2 4/8] mips: octeon: cpu.c: Add table for selective swapping In-Reply-To: <20200820053543.2801672-1-sr@denx.de> References: <20200820053543.2801672-1-sr@denx.de> Message-ID: <20200820053543.2801672-5-sr@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Import octeon_should_swizzle_table[] which is needed for the area specific swapping. It will be used by the platform specific mangle-port.h header. Imported from Linux v5.7. Signed-off-by: Stefan Roese --- (no changes since v1) arch/mips/mach-octeon/cpu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/mips/mach-octeon/cpu.c b/arch/mips/mach-octeon/cpu.c index 2680a2e6ed..6f87a4ef8c 100644 --- a/arch/mips/mach-octeon/cpu.c +++ b/arch/mips/mach-octeon/cpu.c @@ -13,6 +13,27 @@ DECLARE_GLOBAL_DATA_PTR; +/* + * TRUE for devices having registers with little-endian byte + * order, FALSE for registers with native-endian byte order. + * PCI mandates little-endian, USB and SATA are configurable, + * but we chose little-endian for these. + * + * This table will be referened in the Octeon platform specific + * mangle-port.h header. + */ +const bool octeon_should_swizzle_table[256] = { + [0x00] = true, /* bootbus/CF */ + [0x1b] = true, /* PCI mmio window */ + [0x1c] = true, /* PCI mmio window */ + [0x1d] = true, /* PCI mmio window */ + [0x1e] = true, /* PCI mmio window */ + [0x68] = true, /* OCTEON III USB */ + [0x69] = true, /* OCTEON III USB */ + [0x6c] = true, /* OCTEON III SATA */ + [0x6f] = true, /* OCTEON II USB */ +}; + static int get_clocks(void) { const u64 ref_clock = PLL_REF_CLK; -- 2.28.0