[PATCH 1/4] clk: clk-imx8mm: Add flexspi clock and fix set parent

[Lukasz Majewski <lukma@denx.de>]

Hi Peng,

I'm trying to prepare a clk repository PR. It looks like Fabio had some
comments for following series:

https://patchwork.ozlabs.org/project/uboot/patch/20200503125956.6244-1-peng.fan at nxp.com/

Peng, do you plan to resend it shortly?

If yes - please rebase it on top for following tree:
https://github.com/lmajewski/u-boot-dfu/commits/testing

And repost it to ML.

Thanks in advance.

> From: Ye Li <ye.li@nxp.com>
> 
> Add flexspi relevant clocks, and fix set parent clock,  so we can
> assign clocks through DTB
> 
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  drivers/clk/imx/clk-imx8mm.c | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mm.c
> b/drivers/clk/imx/clk-imx8mm.c index fc41a028f6..95069e7395 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -118,6 +118,9 @@ static const char *imx8mm_wdog_sels[] =
> {"clock-osc-24m", "sys_pll1_133m", "sys_ static const char
> *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m",
> "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
> "audio_pll2_clk", "sys_pll1_100m", }; +static const char
> *imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m",
> "sys_pll2_333m", "sys_pll2_500m",
> +					   "audio_pll2_out",
> "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", }; +
>  static ulong imx8mm_clk_get_rate(struct clk *clk)
>  {
>  	struct clk *c;
> @@ -190,7 +193,10 @@ static int imx8mm_clk_set_parent(struct clk
> *clk, struct clk *parent) if (ret)
>  		return ret;
>  
> -	return clk_set_parent(c, cp);
> +	ret = clk_set_parent(c, cp);
> +	c->dev->parent = cp->dev;
> +
> +	return ret;
>  }
>  
>  static struct clk_ops imx8mm_clk_ops = {
> @@ -369,6 +375,8 @@ static int imx8mm_clk_probe(struct udevice *dev)
>  	clk_dm(IMX8MM_CLK_USDHC3,
>  	       imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels,
>  				   base + 0xbc80));
> +	clk_dm(IMX8MM_CLK_QSPI,
> +	       imx8m_clk_composite("qspi", imx8mm_qspi_sels, base +
> 0xab80)); 
>  	clk_dm(IMX8MM_CLK_I2C1_ROOT,
>  	       imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170,
> 0)); @@ -392,6 +400,8 @@ static int imx8mm_clk_probe(struct udevice
> *dev) imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
>  	clk_dm(IMX8MM_CLK_USDHC3_ROOT,
>  	       imx_clk_gate4("usdhc3_root_clk", "usdhc3", base +
> 0x45e0, 0));
> +	clk_dm(IMX8MM_CLK_QSPI_ROOT,
> +	       imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0,
> 0)); 
>  	/* clks not needed in SPL stage */
>  #ifndef CONFIG_SPL_BUILD




Best regards,

Lukasz Majewski

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