* [PATCH 2/4] clk: clk-imx8mn: Update clock tree and support set parent
2020-05-03 12:59 [PATCH 1/4] clk: clk-imx8mm: Add flexspi clock and fix set parent Peng Fan
@ 2020-05-03 12:59 ` Peng Fan
2020-05-03 12:59 ` [PATCH 3/4] clk: imx8mm/8mn: Add USB clocks Peng Fan
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Peng Fan @ 2020-05-03 12:59 UTC (permalink / raw)
To: u-boot
From: Ye Li <ye.li@nxp.com>
Add set clock parent support.
Add ENET and flexspi related clocks to support assigned clocks
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-imx8mn.c | 56 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index eb43971ae6..64aea15a40 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -80,6 +80,17 @@ static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_p
static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
"sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
+#ifndef CONFIG_SPL_BUILD
+static const char *imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
+ "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
+
+static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4", "video_pll1_out", };
+
+static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
+ "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
+#endif
+
static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
"sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
@@ -107,6 +118,9 @@ static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_
static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
"sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
+static const char *imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
+ "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
+
static ulong imx8mn_clk_get_rate(struct clk *clk)
{
struct clk *c;
@@ -164,11 +178,33 @@ static int imx8mn_clk_enable(struct clk *clk)
return __imx8mn_clk_enable(clk, 1);
}
+static int imx8mn_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *cp;
+ int ret;
+
+ debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_id(parent->id, &cp);
+ if (ret)
+ return ret;
+
+ ret = clk_set_parent(c, cp);
+ c->dev->parent = cp->dev;
+
+ return ret;
+}
+
static struct clk_ops imx8mn_clk_ops = {
.set_rate = imx8mn_clk_set_rate,
.get_rate = imx8mn_clk_get_rate,
.enable = imx8mn_clk_enable,
.disable = imx8mn_clk_disable,
+ .set_parent = imx8mn_clk_set_parent,
};
static int imx8mn_clk_probe(struct udevice *dev)
@@ -339,6 +375,8 @@ static int imx8mn_clk_probe(struct udevice *dev)
clk_dm(IMX8MN_CLK_USDHC3,
imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels,
base + 0xbc80));
+ clk_dm(IMX8MN_CLK_QSPI,
+ imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80));
clk_dm(IMX8MN_CLK_I2C1_ROOT,
imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
@@ -362,6 +400,24 @@ static int imx8mn_clk_probe(struct udevice *dev)
imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
clk_dm(IMX8MN_CLK_USDHC3_ROOT,
imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
+ clk_dm(IMX8MN_CLK_QSPI_ROOT,
+ imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
+
+ /* clks not needed in SPL stage */
+#ifndef CONFIG_SPL_BUILD
+ clk_dm(IMX8MN_CLK_ENET_REF,
+ imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels,
+ base + 0xa980));
+ clk_dm(IMX8MN_CLK_ENET_TIMER,
+ imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels,
+ base + 0xaa00));
+ clk_dm(IMX8MN_CLK_ENET_PHY_REF,
+ imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels,
+ base + 0xaa80));
+ clk_dm(IMX8MN_CLK_ENET1_ROOT,
+ imx_clk_gate4("enet1_root_clk", "enet_axi",
+ base + 0x40a0, 0));
+#endif
#ifdef CONFIG_SPL_BUILD
struct clk *clkp, *clkp1;
--
2.16.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 3/4] clk: imx8mm/8mn: Add USB clocks
2020-05-03 12:59 [PATCH 1/4] clk: clk-imx8mm: Add flexspi clock and fix set parent Peng Fan
2020-05-03 12:59 ` [PATCH 2/4] clk: clk-imx8mn: Update clock tree and support " Peng Fan
@ 2020-05-03 12:59 ` Peng Fan
2020-05-03 12:59 ` [PATCH 4/4] clk: imx8mp: Update imx8mp ccf clock driver Peng Fan
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Peng Fan @ 2020-05-03 12:59 UTC (permalink / raw)
To: u-boot
From: Ye Li <ye.li@nxp.com>
Add USB relevant clocks to support usb clock settings for both
DM USB host and gadget drivers
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-imx8mm.c | 17 +++++++++++++++++
drivers/clk/imx/clk-imx8mn.c | 20 ++++++++++++++++++++
2 files changed, 37 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 95069e7395..1db615c355 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -94,6 +94,9 @@ static const char *imx8mm_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "s
static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
"sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
+static const char *imx8mm_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m",
+ "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", };
+
static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
"sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
@@ -121,6 +124,12 @@ static const char *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sy
static const char *imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
"audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
+static const char *imx8mm_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
+ "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
+
+static const char *imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
+ "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
+
static ulong imx8mm_clk_get_rate(struct clk *clk)
{
struct clk *c;
@@ -354,6 +363,8 @@ static int imx8mm_clk_probe(struct udevice *dev)
imx8m_clk_composite_critical("nand_usdhc_bus",
imx8mm_nand_usdhc_sels,
base + 0x8900));
+ clk_dm(IMX8MM_CLK_USB_BUS,
+ imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80));
/* IP */
clk_dm(IMX8MM_CLK_USDHC1,
@@ -377,6 +388,10 @@ static int imx8mm_clk_probe(struct udevice *dev)
base + 0xbc80));
clk_dm(IMX8MM_CLK_QSPI,
imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80));
+ clk_dm(IMX8MM_CLK_USB_CORE_REF,
+ imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100));
+ clk_dm(IMX8MM_CLK_USB_PHY_REF,
+ imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180));
clk_dm(IMX8MM_CLK_I2C1_ROOT,
imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
@@ -402,6 +417,8 @@ static int imx8mm_clk_probe(struct udevice *dev)
imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
clk_dm(IMX8MM_CLK_QSPI_ROOT,
imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
+ clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT,
+ imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
/* clks not needed in SPL stage */
#ifndef CONFIG_SPL_BUILD
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 64aea15a40..c805da1ca3 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -94,6 +94,10 @@ static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "s
static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
"sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
+static const char * const imx8mn_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m",
+ "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
+ "clk_ext4", "audio_pll2_out", };
+
static const char *imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
"sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
@@ -121,6 +125,14 @@ static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sy
static const char *imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
"audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
+static const char * const imx8mn_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+ "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
+ "clk_ext3", "audio_pll2_out", };
+
+static const char * const imx8mn_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+ "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
+ "clk_ext3", "audio_pll2_out", };
+
static ulong imx8mn_clk_get_rate(struct clk *clk)
{
struct clk *c;
@@ -354,6 +366,8 @@ static int imx8mn_clk_probe(struct udevice *dev)
imx8m_clk_composite_critical("nand_usdhc_bus",
imx8mn_nand_usdhc_sels,
base + 0x8900));
+ clk_dm(IMX8MN_CLK_USB_BUS,
+ imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80));
/* IP */
clk_dm(IMX8MN_CLK_USDHC1,
@@ -377,6 +391,10 @@ static int imx8mn_clk_probe(struct udevice *dev)
base + 0xbc80));
clk_dm(IMX8MN_CLK_QSPI,
imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80));
+ clk_dm(IMX8MN_CLK_USB_CORE_REF,
+ imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100));
+ clk_dm(IMX8MN_CLK_USB_PHY_REF,
+ imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180));
clk_dm(IMX8MN_CLK_I2C1_ROOT,
imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
@@ -402,6 +420,8 @@ static int imx8mn_clk_probe(struct udevice *dev)
imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
clk_dm(IMX8MN_CLK_QSPI_ROOT,
imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
+ clk_dm(IMX8MN_CLK_USB1_CTRL_ROOT,
+ imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
/* clks not needed in SPL stage */
#ifndef CONFIG_SPL_BUILD
--
2.16.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 4/4] clk: imx8mp: Update imx8mp ccf clock driver
2020-05-03 12:59 [PATCH 1/4] clk: clk-imx8mm: Add flexspi clock and fix set parent Peng Fan
2020-05-03 12:59 ` [PATCH 2/4] clk: clk-imx8mn: Update clock tree and support " Peng Fan
2020-05-03 12:59 ` [PATCH 3/4] clk: imx8mm/8mn: Add USB clocks Peng Fan
@ 2020-05-03 12:59 ` Peng Fan
2020-05-12 22:32 ` [PATCH 1/4] clk: clk-imx8mm: Add flexspi clock and fix set parent Adam Ford
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Peng Fan @ 2020-05-03 12:59 UTC (permalink / raw)
To: u-boot
From: Ye Li <ye.li@nxp.com>
Add clocks for FEC and flexspi, and add set parent clock callback,
so DTS can assign clocks
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-imx8mp.c | 52 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index a2693d2f7a..787b5750ce 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -79,6 +79,10 @@ static const char *imx8mp_main_axi_sels[] = {"clock-osc-24m", "sys_pll2_333m", "
"sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
"video_pll1_out", "sys_pll1_100m",};
+static const char *imx8mp_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
+ "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
+ "video_pll1_out", "sys_pll3_out", };
+
static const char *imx8mp_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
"sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll1_out", };
@@ -159,10 +163,26 @@ static const char *imx8mp_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_
"vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
"sys_pll1_80m", "sys_pll2_166m" };
+static const char *imx8mp_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m",
+ "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
+ "sys_pll3_out", "sys_pll1_100m", };
+
static const char *imx8mp_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
"audio_pll2_out", "sys_pll1_100m", };
+static const char *imx8mp_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
+ "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
+ "video_pll1_out", "clk_ext4", };
+
+static const char *imx8mp_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out",
+ "clk_ext1", "clk_ext2", "clk_ext3",
+ "clk_ext4", "video_pll1_out", };
+
+static const char *imx8mp_enet_phy_ref_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m",
+ "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out",
+ "video_pll1_out", "audio_pll2_out", };
+
static const char *imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
@@ -223,11 +243,34 @@ static int imx8mp_clk_enable(struct clk *clk)
return __imx8mp_clk_enable(clk, 1);
}
+static int imx8mp_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *cp;
+ int ret;
+
+ debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_id(parent->id, &cp);
+ if (ret)
+ return ret;
+
+ ret = clk_set_parent(c, cp);
+
+ c->dev->parent = cp->dev;
+
+ return ret;
+}
+
static struct clk_ops imx8mp_clk_ops = {
.set_rate = imx8mp_clk_set_rate,
.get_rate = imx8mp_clk_get_rate,
.enable = imx8mp_clk_enable,
.disable = imx8mp_clk_disable,
+ .set_parent = imx8mp_clk_set_parent,
};
static int imx8mp_clk_probe(struct udevice *dev)
@@ -289,6 +332,7 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3));
clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical("main_axi", imx8mp_main_axi_sels, base + 0x8800));
+ clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical("enet_axi", imx8mp_enet_axi_sels, base + 0x8880));
clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900));
clk_dm(IMX8MP_CLK_NOC, imx8m_clk_composite_critical("noc", imx8mp_noc_sels, base + 0x8d00));
clk_dm(IMX8MP_CLK_NOC_IO, imx8m_clk_composite_critical("noc_io", imx8mp_noc_io_sels, base + 0x8d80));
@@ -301,6 +345,10 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080));
clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480));
clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500));
+ clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mp_enet_ref_sels, base + 0xa980));
+ clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite("enet_timer", imx8mp_enet_timer_sels, base + 0xaa00));
+ clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80));
+ clk_dm(IMX8MP_CLK_QSPI, imx8m_clk_composite("qspi", imx8mp_qspi_sels, base + 0xab80));
clk_dm(IMX8MP_CLK_USDHC1, imx8m_clk_composite("usdhc1", imx8mp_usdhc1_sels, base + 0xac00));
clk_dm(IMX8MP_CLK_USDHC2, imx8m_clk_composite("usdhc2", imx8mp_usdhc2_sels, base + 0xac80));
clk_dm(IMX8MP_CLK_I2C1, imx8m_clk_composite("i2c1", imx8mp_i2c1_sels, base + 0xad00));
@@ -321,6 +369,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL));
clk_dm(IMX8MP_CLK_DRAM1_ROOT, imx_clk_gate4_flags("dram1_root_clk", "dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL));
+
+ clk_dm(IMX8MP_CLK_ENET1_ROOT, imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0));
clk_dm(IMX8MP_CLK_GPIO1_ROOT, imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0));
clk_dm(IMX8MP_CLK_GPIO2_ROOT, imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0));
clk_dm(IMX8MP_CLK_GPIO3_ROOT, imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0));
@@ -330,8 +380,10 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
+ clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2("i2c5_root_clk", "i2c5", base + 0x4330, 0));
clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2("i2c6_root_clk", "i2c6", base + 0x4340, 0));
+ clk_dm(IMX8MP_CLK_SIM_ENET_ROOT, imx_clk_gate4("sim_enet_root_clk", "enet_axi", base + 0x4400, 0));
clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
--
2.16.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 1/4] clk: clk-imx8mm: Add flexspi clock and fix set parent
2020-05-03 12:59 [PATCH 1/4] clk: clk-imx8mm: Add flexspi clock and fix set parent Peng Fan
` (2 preceding siblings ...)
2020-05-03 12:59 ` [PATCH 4/4] clk: imx8mp: Update imx8mp ccf clock driver Peng Fan
@ 2020-05-12 22:32 ` Adam Ford
2020-05-12 22:36 ` Fabio Estevam
2020-08-21 11:36 ` Lukasz Majewski
5 siblings, 0 replies; 7+ messages in thread
From: Adam Ford @ 2020-05-12 22:32 UTC (permalink / raw)
To: u-boot
On Sun, May 3, 2020 at 7:37 AM Peng Fan <peng.fan@nxp.com> wrote:
>
> From: Ye Li <ye.li@nxp.com>
>
> Add flexspi relevant clocks, and fix set parent clock, so we can
> assign clocks through DTB
In one place it's called flexspi, but in two other places it's called
QSPI. I recognize that the FlexSPI is controlling a quad-spi nor
flash chip, but isn't there an IP block on some of the i.MX SoC's
called QSPI that is different from FSPI used here?
>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> drivers/clk/imx/clk-imx8mm.c | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
> index fc41a028f6..95069e7395 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -118,6 +118,9 @@ static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_
> static const char *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
> "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
>
> +static const char *imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
> + "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
> +
To reduce confusion, shouldn't the references for FSPI instead of QSPI?
> static ulong imx8mm_clk_get_rate(struct clk *clk)
> {
> struct clk *c;
> @@ -190,7 +193,10 @@ static int imx8mm_clk_set_parent(struct clk *clk, struct clk *parent)
> if (ret)
> return ret;
>
> - return clk_set_parent(c, cp);
> + ret = clk_set_parent(c, cp);
> + c->dev->parent = cp->dev;
> +
> + return ret;
> }
>
> static struct clk_ops imx8mm_clk_ops = {
> @@ -369,6 +375,8 @@ static int imx8mm_clk_probe(struct udevice *dev)
> clk_dm(IMX8MM_CLK_USDHC3,
> imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels,
> base + 0xbc80));
> + clk_dm(IMX8MM_CLK_QSPI,
> + imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80));
>
And also here?
> clk_dm(IMX8MM_CLK_I2C1_ROOT,
> imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
> @@ -392,6 +400,8 @@ static int imx8mm_clk_probe(struct udevice *dev)
> imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
> clk_dm(IMX8MM_CLK_USDHC3_ROOT,
> imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
> + clk_dm(IMX8MM_CLK_QSPI_ROOT,
> + imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
>
> /* clks not needed in SPL stage */
> #ifndef CONFIG_SPL_BUILD
> --
> 2.16.4
>
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 1/4] clk: clk-imx8mm: Add flexspi clock and fix set parent
2020-05-03 12:59 [PATCH 1/4] clk: clk-imx8mm: Add flexspi clock and fix set parent Peng Fan
` (3 preceding siblings ...)
2020-05-12 22:32 ` [PATCH 1/4] clk: clk-imx8mm: Add flexspi clock and fix set parent Adam Ford
@ 2020-05-12 22:36 ` Fabio Estevam
2020-08-21 11:36 ` Lukasz Majewski
5 siblings, 0 replies; 7+ messages in thread
From: Fabio Estevam @ 2020-05-12 22:36 UTC (permalink / raw)
To: u-boot
Hi Peng,
On Sun, May 3, 2020 at 9:37 AM Peng Fan <peng.fan@nxp.com> wrote:
>
> From: Ye Li <ye.li@nxp.com>
>
> Add flexspi relevant clocks, and fix set parent clock, so we can
These are two different changes, which should be addressed by two
separate patches.
Thanks
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 1/4] clk: clk-imx8mm: Add flexspi clock and fix set parent
2020-05-03 12:59 [PATCH 1/4] clk: clk-imx8mm: Add flexspi clock and fix set parent Peng Fan
` (4 preceding siblings ...)
2020-05-12 22:36 ` Fabio Estevam
@ 2020-08-21 11:36 ` Lukasz Majewski
5 siblings, 0 replies; 7+ messages in thread
From: Lukasz Majewski @ 2020-08-21 11:36 UTC (permalink / raw)
To: u-boot
Hi Peng,
I'm trying to prepare a clk repository PR. It looks like Fabio had some
comments for following series:
https://patchwork.ozlabs.org/project/uboot/patch/20200503125956.6244-1-peng.fan at nxp.com/
Peng, do you plan to resend it shortly?
If yes - please rebase it on top for following tree:
https://github.com/lmajewski/u-boot-dfu/commits/testing
And repost it to ML.
Thanks in advance.
> From: Ye Li <ye.li@nxp.com>
>
> Add flexspi relevant clocks, and fix set parent clock, so we can
> assign clocks through DTB
>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> drivers/clk/imx/clk-imx8mm.c | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mm.c
> b/drivers/clk/imx/clk-imx8mm.c index fc41a028f6..95069e7395 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -118,6 +118,9 @@ static const char *imx8mm_wdog_sels[] =
> {"clock-osc-24m", "sys_pll1_133m", "sys_ static const char
> *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m",
> "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
> "audio_pll2_clk", "sys_pll1_100m", }; +static const char
> *imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m",
> "sys_pll2_333m", "sys_pll2_500m",
> + "audio_pll2_out",
> "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", }; +
> static ulong imx8mm_clk_get_rate(struct clk *clk)
> {
> struct clk *c;
> @@ -190,7 +193,10 @@ static int imx8mm_clk_set_parent(struct clk
> *clk, struct clk *parent) if (ret)
> return ret;
>
> - return clk_set_parent(c, cp);
> + ret = clk_set_parent(c, cp);
> + c->dev->parent = cp->dev;
> +
> + return ret;
> }
>
> static struct clk_ops imx8mm_clk_ops = {
> @@ -369,6 +375,8 @@ static int imx8mm_clk_probe(struct udevice *dev)
> clk_dm(IMX8MM_CLK_USDHC3,
> imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels,
> base + 0xbc80));
> + clk_dm(IMX8MM_CLK_QSPI,
> + imx8m_clk_composite("qspi", imx8mm_qspi_sels, base +
> 0xab80));
> clk_dm(IMX8MM_CLK_I2C1_ROOT,
> imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170,
> 0)); @@ -392,6 +400,8 @@ static int imx8mm_clk_probe(struct udevice
> *dev) imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
> clk_dm(IMX8MM_CLK_USDHC3_ROOT,
> imx_clk_gate4("usdhc3_root_clk", "usdhc3", base +
> 0x45e0, 0));
> + clk_dm(IMX8MM_CLK_QSPI_ROOT,
> + imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0,
> 0));
> /* clks not needed in SPL stage */
> #ifndef CONFIG_SPL_BUILD
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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