public inbox for u-boot@lists.denx.de
 help / color / mirror / Atom feed
From: Simon Glass <sjg@chromium.org>
To: u-boot@lists.denx.de
Subject: [PATCH v3 25/57] x86: acpi: Support generation of the DBG2 table
Date: Sun,  6 Sep 2020 15:43:33 -0600	[thread overview]
Message-ID: <20200906214405.71632-9-sjg@chromium.org> (raw)
In-Reply-To: <20200906214405.71632-1-sjg@chromium.org>

Add an implementation of the DBG2 (Debug Port Table 2) ACPI table.
Adjust one of the header includes to be in the correct order, before
adding more.

Note that the DBG2 table is generic but the PCI UART is x86-specific at
present since it assumes an ns16550 UART. It can be generalised later
if necessary.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

(no changes since v1)

Changes in v1:
- Move ASL_REVISION define into this patch
- Move acpi_create_dbg2() into generic code
- Update commit message

 arch/x86/include/asm/acpi_table.h | 11 ++++++
 arch/x86/lib/acpi_table.c         | 41 ++++++++++++++++++++
 include/acpi/acpi_table.h         | 40 +++++++++++++++++++
 lib/acpi/acpi_table.c             | 64 +++++++++++++++++++++++++++++++
 4 files changed, 156 insertions(+)

diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index 7047ee6c772..1b7ff509516 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -46,6 +46,17 @@ u32 acpi_fill_csrt(u32 current);
  */
 int acpi_write_hpet(struct acpi_ctx *ctx);
 
+/**
+ * acpi_write_dbg2_pci_uart() - Write out a DBG2 table
+ *
+ * @ctx: Current ACPI context
+ * @dev: Debug UART device to describe
+ * @access_size: Access size for UART (e.g. ACPI_ACCESS_SIZE_DWORD_ACCESS)
+ * @return 0 if OK, -ve on error
+ */
+int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
+			     uint access_size);
+
 /**
  * acpi_create_gnvs() - Create a GNVS (Global Non Volatile Storage) table
  *
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index e1900ffe42f..28a27103342 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -15,6 +15,7 @@
 #include <serial.h>
 #include <version.h>
 #include <acpi/acpigen.h>
+#include <acpi/acpi_device.h>
 #include <acpi/acpi_table.h>
 #include <asm/acpi/global_nvs.h>
 #include <asm/ioapic.h>
@@ -575,3 +576,43 @@ int acpi_write_hpet(struct acpi_ctx *ctx)
 
 	return 0;
 }
+
+int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
+			     uint access_size)
+{
+	struct acpi_dbg2_header *dbg2 = ctx->current;
+	char path[ACPI_PATH_MAX];
+	struct acpi_gen_regaddr address;
+	phys_addr_t addr;
+	int ret;
+
+	if (!device_active(dev)) {
+		log_info("Device not enabled\n");
+		return -EACCES;
+	}
+	/*
+	 * PCI devices don't remember their resource allocation information in
+	 * U-Boot at present. We assume that MMIO is used for the UART and that
+	 * the address space is 32 bytes: ns16550 uses 8 registers of up to
+	 * 32-bits each. This is only for debugging so it is not a big deal.
+	 */
+	addr = dm_pci_read_bar32(dev, 0);
+	printf("UART addr %lx\n", (ulong)addr);
+
+	memset(&address, '\0', sizeof(address));
+	address.space_id = ACPI_ADDRESS_SPACE_MEMORY;
+	address.addrl = (uint32_t)addr;
+	address.addrh = (uint32_t)((addr >> 32) & 0xffffffff);
+	address.access_size = access_size;
+
+	ret = acpi_device_path(dev, path, sizeof(path));
+	if (ret)
+		return log_msg_ret("path", ret);
+	acpi_create_dbg2(dbg2, ACPI_DBG2_SERIAL_PORT,
+			 ACPI_DBG2_16550_COMPATIBLE, &address, 0x1000, path);
+
+	acpi_inc_align(ctx, dbg2->header.length);
+	acpi_add_table(ctx, dbg2);
+
+	return 0;
+}
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index f8140446a59..c826a797f5b 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -448,6 +448,29 @@ struct __packed acpi_dmar {
 
 #define ACPI_DBG2_UNKNOWN		0x00FF
 
+/* DBG2: Microsoft Debug Port Table 2 header */
+struct __packed acpi_dbg2_header {
+	struct acpi_table_header header;
+	u32 devices_offset;
+	u32 devices_count;
+};
+
+/* DBG2: Microsoft Debug Port Table 2 device entry */
+struct __packed acpi_dbg2_device {
+	u8  revision;
+	u16 length;
+	u8 address_count;
+	u16 namespace_string_length;
+	u16 namespace_string_offset;
+	u16 oem_data_length;
+	u16 oem_data_offset;
+	u16 port_type;
+	u16 port_subtype;
+	u8  reserved[2];
+	u16 base_address_offset;
+	u16 address_size_offset;
+};
+
 /* SPCR (Serial Port Console Redirection table) */
 struct __packed acpi_spcr {
 	struct acpi_table_header header;
@@ -522,6 +545,23 @@ int acpi_get_table_revision(enum acpi_tables table);
  */
 int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags);
 
+/**
+ * acpi_create_dbg2() - Create a DBG2 table
+ *
+ * This table describes how to access the debug UART
+ *
+ * @dbg2: Place to put information
+ * @port_type: Serial port type (see ACPI_DBG2_...)
+ * @port_subtype: Serial port sub-type (see ACPI_DBG2_...)
+ * @address: ACPI address of port
+ * @address_size: Size of address space
+ * @device_path: Path of device (created using acpi_device_path())
+ */
+void acpi_create_dbg2(struct acpi_dbg2_header *dbg2,
+		      int port_type, int port_subtype,
+		      struct acpi_gen_regaddr *address, uint32_t address_size,
+		      const char *device_path);
+
 /**
  * acpi_fill_header() - Set up a new table header
  *
diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c
index acc55e7fad6..908d8903893 100644
--- a/lib/acpi/acpi_table.c
+++ b/lib/acpi/acpi_table.c
@@ -264,3 +264,67 @@ void acpi_setup_base_tables(struct acpi_ctx *ctx, void *start)
 	 */
 	acpi_align64(ctx);
 }
+
+void acpi_create_dbg2(struct acpi_dbg2_header *dbg2,
+		      int port_type, int port_subtype,
+		      struct acpi_gen_regaddr *address, u32 address_size,
+		      const char *device_path)
+{
+	uintptr_t current;
+	struct acpi_dbg2_device *device;
+	u32 *dbg2_addr_size;
+	struct acpi_table_header *header;
+	size_t path_len;
+	const char *path;
+	char *namespace;
+
+	/* Fill out header fields. */
+	current = (uintptr_t)dbg2;
+	memset(dbg2, '\0', sizeof(struct acpi_dbg2_header));
+	header = &dbg2->header;
+
+	header->revision = acpi_get_table_revision(ACPITAB_DBG2);
+	acpi_fill_header(header, "DBG2");
+	header->aslc_revision = ASL_REVISION;
+
+	/* One debug device defined */
+	dbg2->devices_offset = sizeof(struct acpi_dbg2_header);
+	dbg2->devices_count = 1;
+	current += sizeof(struct acpi_dbg2_header);
+
+	/* Device comes after the header */
+	device = (struct acpi_dbg2_device *)current;
+	memset(device, 0, sizeof(struct acpi_dbg2_device));
+	current += sizeof(struct acpi_dbg2_device);
+
+	device->revision = 0;
+	device->address_count = 1;
+	device->port_type = port_type;
+	device->port_subtype = port_subtype;
+
+	/* Base Address comes after device structure */
+	memcpy((void *)current, address, sizeof(struct acpi_gen_regaddr));
+	device->base_address_offset = current - (uintptr_t)device;
+	current += sizeof(struct acpi_gen_regaddr);
+
+	/* Address Size comes after address structure */
+	dbg2_addr_size = (uint32_t *)current;
+	device->address_size_offset = current - (uintptr_t)device;
+	*dbg2_addr_size = address_size;
+	current += sizeof(uint32_t);
+
+	/* Namespace string comes last, use '.' if not provided */
+	path = device_path ? : ".";
+	/* Namespace string length includes NULL terminator */
+	path_len = strlen(path) + 1;
+	namespace = (char *)current;
+	device->namespace_string_length = path_len;
+	device->namespace_string_offset = current - (uintptr_t)device;
+	strncpy(namespace, path, path_len);
+	current += path_len;
+
+	/* Update structure lengths and checksum */
+	device->length = current - (uintptr_t)device;
+	header->length = current - (uintptr_t)dbg2;
+	header->checksum = table_compute_checksum(dbg2, header->length);
+}
-- 
2.28.0.526.ge36021eeef-goog

  parent reply	other threads:[~2020-09-06 21:43 UTC|newest]

Thread overview: 80+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-06 21:43 [PATCH v3 00/57] dm: Add programatic generation of ACPI tables (part D) Simon Glass
2020-09-06 21:43 ` [PATCH v3 01/57] x86: acpi: Add cros_ec tables Simon Glass
2020-09-06 21:43 ` [PATCH v3 02/57] x86: acpi: Add base asl files for common x86 devices Simon Glass
2020-09-21 13:50   ` Wolfgang Wallner
2020-09-22 13:51     ` Simon Glass
2020-09-22 14:19       ` Wolfgang Wallner
2020-09-22 14:30         ` Bin Meng
2020-09-22 14:47           ` Wolfgang Wallner
2020-09-22 14:52             ` Bin Meng
2020-09-06 21:43 ` [PATCH v3 03/57] x86: acpi: apl: Add asl files for Apollo Lake Simon Glass
2020-09-06 21:43 ` [PATCH v3 04/57] x86: acpi: Add DPTF asl files Simon Glass
2020-09-06 21:43 ` [PATCH v3 05/57] x86: apl: Correct PCIE_ECAM_BASE Simon Glass
2020-09-22  7:30   ` Bin Meng
2020-09-06 21:43 ` [PATCH v3 06/57] x86: Add a config for the systemagent PCIEX regions size Simon Glass
2020-09-06 21:43 ` [PATCH v3 07/57] x86: Add a common global NVS structure Simon Glass
2020-09-06 21:43 ` [PATCH v3 08/57] x86: acpi: Support external GNVS tables Simon Glass
2020-09-06 21:43 ` [PATCH v3 09/57] x86: acpi: Expand the GNVS Simon Glass
2020-09-06 21:43 ` [PATCH v3 10/57] x86: coral: Add ACPI tables for coral Simon Glass
2020-09-06 21:43 ` [PATCH v3 11/57] acpi: Add support for writing a _PRW Simon Glass
2020-09-06 21:43 ` [PATCH v3 12/57] acpi: Add support for conditions and return values Simon Glass
2020-09-06 21:43 ` [PATCH v3 13/57] acpi: Support generating a multi-function _DSM for devices Simon Glass
2020-09-06 21:43 ` [PATCH v3 14/57] dm: acpi: Use correct GPIO polarity type in acpi_dp_add_gpio() Simon Glass
2020-09-06 21:43 ` [PATCH v3 15/57] x86: link: Allow more space for U-Boot Simon Glass
2020-09-22  7:44   ` Bin Meng
2020-09-06 21:43 ` [PATCH v3 16/57] i2c: Add a generic driver to generate ACPI info Simon Glass
2020-09-06 21:43 ` [PATCH v3 17/57] x86: Add wake sources for the acpi_gpe driver Simon Glass
2020-09-06 21:43 ` [PATCH v3 18/57] x86: apl: Support writing the IntelGraphicsMem table Simon Glass
2020-09-06 21:43 ` [PATCH v3 19/57] x86: acpi: Add a common routine to write WiFi info Simon Glass
2020-09-06 21:43 ` [PATCH v3 20/57] x86: Add some definitions for SMM Simon Glass
2020-09-06 21:43 ` [PATCH v3 21/57] x86: apl: Add power-management definitions Simon Glass
2020-09-06 21:43 ` [PATCH v3 22/57] x86: apl: Update iomap for ACPI Simon Glass
2020-09-06 21:43 ` [PATCH v3 23/57] x86: Add a few common Intel CPU functions Simon Glass
2020-09-06 21:43 ` [PATCH v3 24/57] x86: acpi: Support generation of the HPET table Simon Glass
2020-09-06 21:43 ` Simon Glass [this message]
2020-09-06 21:43 ` [PATCH v3 26/57] acpi: Add support for generating processor tables Simon Glass
2020-09-06 21:43 ` [PATCH v3 27/57] x86: acpi: Add PCT and PTC tables Simon Glass
2020-09-06 21:43 ` [PATCH v3 28/57] acpi: Add more support for generating processor tables Simon Glass
2020-09-06 21:43 ` [PATCH v3 29/57] x86: acpi: Add common Intel ACPI tables Simon Glass
2020-09-06 21:43 ` [PATCH v3 30/57] x86: Support Atom SoCs using SWSMISCI rather than the SWSCI Simon Glass
2020-09-06 21:43 ` [PATCH v3 31/57] x86: acpi: Add support for additional Intel tables Simon Glass
2020-09-06 21:43 ` [PATCH v3 32/57] x86: apl: Allow reading hostbridge base addresses Simon Glass
2020-09-06 21:43 ` [PATCH v3 33/57] p2sb: Add some definitions used for ACPI Simon Glass
2020-09-06 21:43 ` [PATCH v3 34/57] x86: apl: Generate required ACPI tables Simon Glass
2020-09-06 21:43 ` [PATCH v3 35/57] x86: apl: Add support for hostbridge ACPI generation Simon Glass
2020-09-06 21:43 ` [PATCH v3 36/57] x86: apl: Generate CPU tables Simon Glass
2020-09-06 21:43 ` [PATCH v3 37/57] x86: apl: Generate ACPI table for LPC Simon Glass
2020-09-06 21:43 ` [PATCH v3 38/57] x86: apl: Drop unnecessary code in PMC driver Simon Glass
2020-09-06 21:43 ` [PATCH v3 39/57] tpm: cr50: Add ACPI support Simon Glass
2020-09-21 11:50   ` Andy Shevchenko
2020-09-21 11:53     ` Andy Shevchenko
2020-09-22  8:15     ` Bin Meng
2020-09-22  8:27     ` Andy Shevchenko
2020-09-06 21:43 ` [PATCH v3 40/57] x86: fsp: Update the FSP API with the end-firmware method Simon Glass
2020-09-22  7:58   ` Bin Meng
2020-09-06 21:43 ` [PATCH v3 41/57] x86: cpu: Report address width from cpu_get_info() Simon Glass
2020-09-06 21:43 ` [PATCH v3 42/57] x86: Sort the MTRR table Simon Glass
2020-09-06 21:43 ` [PATCH v3 43/57] x86: Notify the FSP of the 'end firmware' event Simon Glass
2020-09-06 21:43 ` [PATCH v3 44/57] x86: Correct the assembly guard in e820.h Simon Glass
2020-09-22  8:02   ` Bin Meng
2020-09-06 21:43 ` [PATCH v3 45/57] x86: Add a header guard to asm/acpi_table.h Simon Glass
2020-09-22  8:03   ` Bin Meng
2020-09-06 21:43 ` [PATCH v3 46/57] x86: Correct handling of MADT table CPUs Simon Glass
2020-09-06 21:43 ` [PATCH v3 47/57] acpi: tpm: Add a TPM2 table Simon Glass
2020-09-06 21:43 ` [PATCH v3 48/57] acpi: tpm: Add a TPM1 table Simon Glass
2020-09-06 21:43 ` [PATCH v3 49/57] x86: acpi: Set the log category for x86 table generation Simon Glass
2020-09-22  8:04   ` Bin Meng
2020-09-06 21:43 ` [PATCH v3 50/57] x86: coral: Add audio descriptor files Simon Glass
2020-09-06 21:43 ` [PATCH v3 51/57] x86: apl: Check low-level init in FSP-S pre-init Simon Glass
2020-09-06 21:44 ` [PATCH v3 52/57] x86: fsp: Add more debugging for silicon init Simon Glass
2020-09-22  8:06   ` Bin Meng
2020-09-06 21:44 ` [PATCH v3 53/57] x86: fsp: Show FSP-S or FSP-M address in fsp_get_header() Simon Glass
2020-09-22  8:06   ` Bin Meng
2020-09-06 21:44 ` [PATCH v3 54/57] acpi: Use defines for field lengths Simon Glass
2020-09-22  8:07   ` Bin Meng
2020-09-06 21:44 ` [PATCH v3 55/57] x86: Add a way to add to the e820 memory table Simon Glass
2020-09-22  8:09   ` Bin Meng
2020-09-06 21:44 ` [PATCH v3 56/57] x86: Move include of bitops out of ACPI region Simon Glass
2020-09-22  8:09   ` Bin Meng
2020-09-06 21:44 ` [PATCH v3 57/57] x86: coral: Update config and device tree for ACPI Simon Glass
2020-09-22  8:16 ` [PATCH v3 00/57] dm: Add programatic generation of ACPI tables (part D) Bin Meng

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200906214405.71632-9-sjg@chromium.org \
    --to=sjg@chromium.org \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox