[PATCH 2/2] ram: add ddr4 dual x8 configuration

Ryan Chen
2020-09-21T02:42:07Z

> -----Original Message-----
> From: Dylan Hung <dylan_hung@aspeedtech.com>
> Sent: Monday, September 7, 2020 4:25 PM
> To: Ryan Chen <ryan_chen@aspeedtech.com>; u-boot at lists.denx.de
> Cc: BMC-SW <BMC-SW@aspeedtech.com>
> Subject: [PATCH 2/2] ram: add ddr4 dual x8 configuration
>
> the aspeed ddr sdram controller needs to know if the memory chip mounted
> on the board is dual x8 die or not. Or it may get the wrong size of the memory
> space.
>
> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>

Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>

> ---
> drivers/ram/Kconfig | 1 +
> drivers/ram/aspeed/Kconfig | 10 ++++++++++
> drivers/ram/aspeed/sdram_ast2500.c | 2 +-
> 3 files changed, 12 insertions(+), 1 deletion(-) create mode 100644
> drivers/ram/aspeed/Kconfig
>
> diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index
> 7e6e981897..d277237288 100644
> --- a/drivers/ram/Kconfig
> +++ b/drivers/ram/Kconfig
> @@ -76,3 +76,4 @@ config IMXRT_SDRAM
> source "drivers/ram/rockchip/Kconfig"
> source "drivers/ram/sifive/Kconfig"
> source "drivers/ram/stm32mp1/Kconfig"
> +source "drivers/ram/aspeed/Kconfig"
> diff --git a/drivers/ram/aspeed/Kconfig b/drivers/ram/aspeed/Kconfig new file
> mode 100644 index 0000000000..020c913188
> --- /dev/null
> +++ b/drivers/ram/aspeed/Kconfig
> @@ -0,0 +1,10 @@
> +if RAM || SPL_RAM
> +config ASPEED_DDR4_DUALX8
> + bool "Enable Dual X8 DDR4 die"
> + depends on DM && OF_CONTROL && ARCH_ASPEED
> + default n
> + help
> + Say Y if dual X8 DDR4 die is used on the board. The aspeed ddr
> sdram
> + controller needs to know if the memory chip mounted on the board
> is dual
> + x8 die or not. Or it may get the wrong size of the memory space.
> +endif
> diff --git a/drivers/ram/aspeed/sdram_ast2500.c
> b/drivers/ram/aspeed/sdram_ast2500.c
> index a3adaa8a99..8bfbf562c3 100644
> --- a/drivers/ram/aspeed/sdram_ast2500.c
> +++ b/drivers/ram/aspeed/sdram_ast2500.c
> @@ -247,7 +247,7 @@ static int ast2500_sdrammc_init_ddr4(struct
> dram_info *info)
> | SDRAM_PCR_RESETN_DIS
> | SDRAM_PCR_RGAP_CTRL_EN | SDRAM_PCR_ODT_EN |
> SDRAM_PCR_ODT_EXT_EN;
> const u32 conf = (SDRAM_CONF_CAP_1024M <<
> SDRAM_CONF_CAP_SHIFT) -#ifdef CONFIG_DUALX8_RAM
> +#ifdef CONFIG_ASPEED_DDR4_DUALX8
> | SDRAM_CONF_DUALX8
> #endif
> | SDRAM_CONF_SCRAMBLE | SDRAM_CONF_SCRAMBLE_PAT2 |
> SDRAM_CONF_DDR4;
> --
> 2.17.1