From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sean Anderson Date: Mon, 7 Sep 2020 14:16:53 -0400 Subject: [PATCH 1/7] Revert "riscv: Clear pending interrupts before enabling IPIs" In-Reply-To: <20200907181659.92449-1-seanga2@gmail.com> References: <20200907181659.92449-1-seanga2@gmail.com> Message-ID: <20200907181659.92449-2-seanga2@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Clearing MIP doesn't do anything. Whoops. The following commits should tackle this problem in a more robust manner. This reverts commit 9472630337e7c4ac442066b5a752aaa8c3b4d4a6. Signed-off-by: Sean Anderson --- arch/riscv/cpu/start.S | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index bf9fdf369b..e3222b1ea7 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -65,8 +65,6 @@ _start: #else li t0, SIE_SSIE #endif - /* Clear any pending IPIs */ - csrc MODE_PREFIX(ip), t0 csrs MODE_PREFIX(ie), t0 #endif -- 2.28.0