From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sean Anderson Date: Mon, 7 Sep 2020 14:16:54 -0400 Subject: [PATCH 2/7] riscv: Match memory barriers between send_ipi_many and handle_ipi In-Reply-To: <20200907181659.92449-1-seanga2@gmail.com> References: <20200907181659.92449-1-seanga2@gmail.com> Message-ID: <20200907181659.92449-3-seanga2@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Without a matching barrier on the write side, the barrier in handle_ipi does nothing. It was entirely possible for the boot hart to write to addr, arg0, and arg1 *after* sending the IPI, because there was no barrier on the sending side. Fixes: 90ae28143700bae4edd23930a7772899ad259058 Signed-off-by: Sean Anderson --- arch/riscv/lib/smp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index ac22136314..ab6d8bd7fa 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -54,6 +54,8 @@ static int send_ipi_many(struct ipi_data *ipi, int wait) gd->arch.ipi[reg].arg0 = ipi->arg0; gd->arch.ipi[reg].arg1 = ipi->arg1; + __smp_mb(); + ret = riscv_send_ipi(reg); if (ret) { pr_err("Cannot send IPI to hart %d\n", reg); -- 2.28.0