[PATCH v2 0/7] riscv: Correctly handle IPIs already pending upon boot

Sean Anderson
2020-09-14T14:22:56Z

On the K210, the prior stage bootloader does not clear IPIs. This presents
a problem, because U-Boot up until this point assumes (with one exception)
that IPIs are cleared when it starts. This series attempts to fix this in a
robust manner, and fix several concurrency bugs I noticed while fixing
these other areas. Heinrich previously submitted a patch addressing part of
this problem in [1].

[1] https://patchwork.ozlabs.org/project/uboot/patch/20200811035648.3284-1-xypron.glpk at gmx.de/

Changes in v2:
- Use a valid bit instead of addr to validate IPIs
- Make riscv_ipi_init_secondary_hart static
- Remove fences after amoswaps
- Set gp early with XIP
- Clarify comments regarding tp

Sean Anderson (7):
Revert "riscv: Clear pending interrupts before enabling IPIs"
riscv: Match memory barriers between send_ipi_many and handle_ipi
riscv: Use a valid bit to ignore already-pending IPIs
riscv: Clear pending IPIs on initialization
riscv: Consolidate fences into AMOs for available_harts_lock
riscv: Ensure gp is NULL or points to valid data
riscv: Add some comments to start.S

arch/riscv/cpu/cpu.c | 18 ++++++++++++
arch/riscv/cpu/start.S | 56 +++++++++++++++++++++++++++---------
arch/riscv/include/asm/smp.h | 7 +++++
arch/riscv/lib/interrupts.c | 3 +-
arch/riscv/lib/smp.c | 16 ++++++++++-
5 files changed, 85 insertions(+), 15 deletions(-)

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2.28.0