From: Sean Anderson <seanga2@gmail.com>
To: u-boot@lists.denx.de
Subject: [PATCH v6 5/9] riscv: Clean up initialization in Andes PLIC
Date: Mon, 28 Sep 2020 10:52:25 -0400 [thread overview]
Message-ID: <20200928145229.449782-6-seanga2@gmail.com> (raw)
In-Reply-To: <20200928145229.449782-1-seanga2@gmail.com>
This merges the PLIC initialization code from two functions into one.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
---
This patch builds but has NOT been tested.
(no changes since v1)
arch/riscv/lib/andes_plic.c | 58 ++++++++++++++++---------------------
1 file changed, 25 insertions(+), 33 deletions(-)
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index c2a8fe4d9e..267d6a191b 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -41,53 +41,45 @@ static int enable_ipi(int hart)
return 0;
}
-static int init_plic(void)
+int riscv_init_ipi(void)
{
- struct udevice *dev;
- ofnode node;
int ret;
+ long *base = syscon_get_first_range(RISCV_SYSCON_PLIC);
+ ofnode node;
+ struct udevice *dev;
u32 reg;
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+ gd->arch.plic = base;
+
ret = uclass_find_first_device(UCLASS_CPU, &dev);
if (ret)
return ret;
+ else if (!dev)
+ return -ENODEV;
- if (dev) {
- ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
- const char *device_type;
+ ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
+ const char *device_type;
- device_type = ofnode_read_string(node, "device_type");
- if (!device_type)
- continue;
+ device_type = ofnode_read_string(node, "device_type");
+ if (!device_type)
+ continue;
- if (strcmp(device_type, "cpu"))
- continue;
+ if (strcmp(device_type, "cpu"))
+ continue;
- /* skip if hart is marked as not available */
- if (!ofnode_is_available(node))
- continue;
+ /* skip if hart is marked as not available */
+ if (!ofnode_is_available(node))
+ continue;
- /* read hart ID of CPU */
- ret = ofnode_read_u32(node, "reg", ®);
- if (ret == 0)
- enable_ipi(reg);
- }
-
- return 0;
+ /* read hart ID of CPU */
+ ret = ofnode_read_u32(node, "reg", ®);
+ if (ret == 0)
+ enable_ipi(reg);
}
- return -ENODEV;
-}
-
-int riscv_init_ipi(void)
-{
- long *ret = syscon_get_first_range(RISCV_SYSCON_PLIC);
-
- if (IS_ERR(ret))
- return PTR_ERR(ret);
- gd->arch.plic = ret;
-
- return init_plic();
+ return 0;
}
int riscv_send_ipi(int hart)
--
2.28.0
next prev parent reply other threads:[~2020-09-28 14:52 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-28 14:52 [PATCH v6 0/9] riscv: Clean up timer drivers Sean Anderson
2020-09-28 14:52 ` [PATCH v6 1/9] riscv: Rework riscv timer driver to only support S-mode Sean Anderson
2020-09-28 14:52 ` [PATCH v6 2/9] timer: Add helper for drivers using timebase fallback Sean Anderson
2020-09-28 14:52 ` [PATCH v6 3/9] timer: Add a test for timer_timebase_fallback Sean Anderson
2020-09-28 14:52 ` [PATCH v6 4/9] riscv: Rework Andes PLMT as a UCLASS_TIMER driver Sean Anderson
2020-09-28 14:52 ` Sean Anderson [this message]
2020-09-28 14:52 ` [PATCH v6 6/9] riscv: Rework Sifive CLINT as " Sean Anderson
2020-09-28 14:52 ` [PATCH v6 7/9] riscv: clk: Add CLINT clock to kendryte clock driver Sean Anderson
2020-09-28 14:52 ` [PATCH v6 8/9] riscv: Update Kendryte device tree for new CLINT driver Sean Anderson
2020-09-28 14:52 ` [PATCH v6 9/9] riscv: Update SiFive " Sean Anderson
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