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From: Sean Anderson <seanga2@gmail.com>
To: u-boot@lists.denx.de
Subject: [PATCH v6 7/9] riscv: clk: Add CLINT clock to kendryte clock driver
Date: Mon, 28 Sep 2020 10:52:27 -0400	[thread overview]
Message-ID: <20200928145229.449782-8-seanga2@gmail.com> (raw)
In-Reply-To: <20200928145229.449782-1-seanga2@gmail.com>

Another "virtual" clock (in the sense that it isn't configurable). This
could possibly be done as a clock in the device tree, but I think this is a
bit cleaner.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---
checkpatch still complains about this one, but I don't see any reason to
break it up even further. It doesn't make sense to me to split the header
file change from everything else.

(no changes since v2)

Changes in v2:
- Split Kendryte binding changes into their own commit

 drivers/clk/kendryte/clk.c              | 4 ++++
 include/dt-bindings/clock/k210-sysctl.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
index 981b3b7699..bb196961af 100644
--- a/drivers/clk/kendryte/clk.c
+++ b/drivers/clk/kendryte/clk.c
@@ -646,6 +646,10 @@ static int k210_clk_probe(struct udevice *dev)
 	REGISTER_GATE(K210_CLK_RTC,   "rtc",   in0);
 #undef REGISTER_GATE
 
+	/* The MTIME register in CLINT runs at one 50th the CPU clock speed */
+	clk_dm(K210_CLK_CLINT,
+	       clk_register_fixed_factor(NULL, "clint", "cpu", 0, 1, 50));
+
 	return 0;
 }
 
diff --git a/include/dt-bindings/clock/k210-sysctl.h b/include/dt-bindings/clock/k210-sysctl.h
index 0e3ed3fb9f..fe852bbd92 100644
--- a/include/dt-bindings/clock/k210-sysctl.h
+++ b/include/dt-bindings/clock/k210-sysctl.h
@@ -55,5 +55,6 @@
 #define K210_CLK_OTP    43
 #define K210_CLK_RTC    44
 #define K210_CLK_ACLK   45
+#define K210_CLK_CLINT  46
 
 #endif /* CLOCK_K210_SYSCTL_H */
-- 
2.28.0

  parent reply	other threads:[~2020-09-28 14:52 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-28 14:52 [PATCH v6 0/9] riscv: Clean up timer drivers Sean Anderson
2020-09-28 14:52 ` [PATCH v6 1/9] riscv: Rework riscv timer driver to only support S-mode Sean Anderson
2020-09-28 14:52 ` [PATCH v6 2/9] timer: Add helper for drivers using timebase fallback Sean Anderson
2020-09-28 14:52 ` [PATCH v6 3/9] timer: Add a test for timer_timebase_fallback Sean Anderson
2020-09-28 14:52 ` [PATCH v6 4/9] riscv: Rework Andes PLMT as a UCLASS_TIMER driver Sean Anderson
2020-09-28 14:52 ` [PATCH v6 5/9] riscv: Clean up initialization in Andes PLIC Sean Anderson
2020-09-28 14:52 ` [PATCH v6 6/9] riscv: Rework Sifive CLINT as UCLASS_TIMER driver Sean Anderson
2020-09-28 14:52 ` Sean Anderson [this message]
2020-09-28 14:52 ` [PATCH v6 8/9] riscv: Update Kendryte device tree for new CLINT driver Sean Anderson
2020-09-28 14:52 ` [PATCH v6 9/9] riscv: Update SiFive " Sean Anderson

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