From: Sean Anderson <seanga2@gmail.com>
To: u-boot@lists.denx.de
Subject: [PATCH v6 8/9] riscv: Update Kendryte device tree for new CLINT driver
Date: Mon, 28 Sep 2020 10:52:28 -0400 [thread overview]
Message-ID: <20200928145229.449782-9-seanga2@gmail.com> (raw)
In-Reply-To: <20200928145229.449782-1-seanga2@gmail.com>
The interrupt controller property is removed from the clint binding because
the clint is not an interrupt-controller. That is, no other devices have an
interrupt which is controlled by the clint.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
---
(no changes since v4)
Changes in v4:
- Remove clock-frequency property from k210 clint binding because we fall
back on timebase-frequency
Changes in v2:
- New
arch/riscv/dts/k210.dtsi | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
index 2546c7d4e0..84cff51c36 100644
--- a/arch/riscv/dts/k210.dtsi
+++ b/arch/riscv/dts/k210.dtsi
@@ -17,6 +17,8 @@
compatible = "kendryte,k210";
aliases {
+ cpu0 = &cpu0;
+ cpu1 = &cpu1;
dma0 = &dmac0;
gpio0 = &gpio0;
gpio1 = &gpio1_0;
@@ -126,14 +128,13 @@
read-only;
};
- clint0: interrupt-controller at 2000000 {
+ clint0: clint at 2000000 {
#interrupt-cells = <1>;
compatible = "kendryte,k210-clint", "riscv,clint0";
reg = <0x2000000 0xC000>;
- interrupt-controller;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
<&cpu1_intc 3>, <&cpu1_intc 7>;
- clocks = <&sysclk K210_CLK_CPU>;
+ clocks = <&sysclk K210_CLK_CLINT>;
};
plic0: interrupt-controller at C000000 {
--
2.28.0
next prev parent reply other threads:[~2020-09-28 14:52 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-28 14:52 [PATCH v6 0/9] riscv: Clean up timer drivers Sean Anderson
2020-09-28 14:52 ` [PATCH v6 1/9] riscv: Rework riscv timer driver to only support S-mode Sean Anderson
2020-09-28 14:52 ` [PATCH v6 2/9] timer: Add helper for drivers using timebase fallback Sean Anderson
2020-09-28 14:52 ` [PATCH v6 3/9] timer: Add a test for timer_timebase_fallback Sean Anderson
2020-09-28 14:52 ` [PATCH v6 4/9] riscv: Rework Andes PLMT as a UCLASS_TIMER driver Sean Anderson
2020-09-28 14:52 ` [PATCH v6 5/9] riscv: Clean up initialization in Andes PLIC Sean Anderson
2020-09-28 14:52 ` [PATCH v6 6/9] riscv: Rework Sifive CLINT as UCLASS_TIMER driver Sean Anderson
2020-09-28 14:52 ` [PATCH v6 7/9] riscv: clk: Add CLINT clock to kendryte clock driver Sean Anderson
2020-09-28 14:52 ` Sean Anderson [this message]
2020-09-28 14:52 ` [PATCH v6 9/9] riscv: Update SiFive device tree for new CLINT driver Sean Anderson
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