From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sean Anderson Date: Tue, 29 Sep 2020 10:18:26 -0400 Subject: [PATCH 01/10] clk: k210: Fix PLLs not being enabled In-Reply-To: <20200929141835.38435-1-seanga2@gmail.com> References: <20200929141835.38435-1-seanga2@gmail.com> Message-ID: <20200929141835.38435-2-seanga2@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de After starting or setting the rate of a PLL, the enable bit must be set. This fixes a bug where the AI ram would not be accessible, because it requires PLL1 to be running. Signed-off-by: Sean Anderson --- drivers/clk/kendryte/pll.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c index ab6d75d585..f198920113 100644 --- a/drivers/clk/kendryte/pll.c +++ b/drivers/clk/kendryte/pll.c @@ -531,6 +531,7 @@ static int k210_pll_enable(struct clk *clk) k210_pll_waitfor_lock(pll); reg &= ~K210_PLL_BYPASS; + reg |= K210_PLL_EN; writel(reg, pll->reg); return 0; @@ -550,6 +551,7 @@ static int k210_pll_disable(struct clk *clk) writel(reg, pll->reg); reg &= ~K210_PLL_PWRD; + reg &= ~K210_PLL_EN; writel(reg, pll->reg); return 0; } -- 2.28.0