From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sean Anderson Date: Tue, 29 Sep 2020 10:18:32 -0400 Subject: [PATCH 07/10] ram: sifive: Default to y only if compiling for fu540 In-Reply-To: <20200929141835.38435-1-seanga2@gmail.com> References: <20200929141835.38435-1-seanga2@gmail.com> Message-ID: <20200929141835.38435-8-seanga2@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Other RISC-V targets should not have RAM_SIFIVE enabled by default. Signed-off-by: Sean Anderson --- drivers/ram/sifive/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig index 6aca22ab2a..b24153d971 100644 --- a/drivers/ram/sifive/Kconfig +++ b/drivers/ram/sifive/Kconfig @@ -1,7 +1,7 @@ config RAM_SIFIVE bool "Ram drivers support for SiFive SoCs" depends on RAM && RISCV - default y + default y if TARGET_SIFIVE_FU540 help This enables support for ram drivers of SiFive SoCs. -- 2.28.0