[PATCH v2 0/3] riscv: Move timers into drivers/timer

[PATCH v2 0/3] riscv: Move timers into drivers/timer

[Sean Anderson]

Now that mtime sources are regular timers, they can go in with the rest of the
timer drivers. I have assigned maintenance of these drivers to Rick Chen, as
they were previous under his purview.

Passing CI (for v1) located at [1].

[1] https://dev.azure.com/seanga2/9603e4b8-6f49-4106-b8fc-46e66a869d69/_build/results?buildId=45

Changes in v2:
- Rebase onto master

Sean Anderson (3):
  riscv: Move Andes PLMT driver to drivers/timer
  timer: Add _TIMER suffix to Andes PLMT Kconfig
  riscv: Move timer portions of SiFive CLINT to drivers/timer

 MAINTAINERS                                   |  2 +
 arch/riscv/Kconfig                            |  7 ---
 arch/riscv/cpu/ax25/Kconfig                   |  2 +-
 arch/riscv/lib/Makefile                       |  1 -
 arch/riscv/lib/sifive_clint.c                 | 41 +---------------
 drivers/timer/Kconfig                         |  7 +++
 drivers/timer/Makefile                        |  2 +
 .../timer/andes_plmt_timer.c                  |  0
 drivers/timer/sifive_clint_timer.c            | 47 +++++++++++++++++++
 9 files changed, 61 insertions(+), 48 deletions(-)
 rename arch/riscv/lib/andes_plmt.c => drivers/timer/andes_plmt_timer.c (100%)
 create mode 100644 drivers/timer/sifive_clint_timer.c

-- 
2.28.0

[PATCH v2 1/3] riscv: Move Andes PLMT driver to drivers/timer

[Sean Anderson]

This is a regular timer driver, and should live with the other timer
drivers.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
---

(no changes since v1)

 MAINTAINERS                                                | 1 +
 arch/riscv/Kconfig                                         | 7 -------
 arch/riscv/lib/Makefile                                    | 1 -
 drivers/timer/Kconfig                                      | 7 +++++++
 drivers/timer/Makefile                                     | 1 +
 .../lib/andes_plmt.c => drivers/timer/andes_plmt_timer.c   | 0
 6 files changed, 9 insertions(+), 8 deletions(-)
 rename arch/riscv/lib/andes_plmt.c => drivers/timer/andes_plmt_timer.c (100%)

diff --git a/MAINTAINERS b/MAINTAINERS
index fc4fad46ee..5d022352c4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -938,6 +938,7 @@ S:	Maintained
 T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-riscv.git
 F:	arch/riscv/
 F:	cmd/riscv/
+F:	drivers/timer/andes_plmt_timer.c
 F:	tools/prelink-riscv.c
 
 RISC-V KENDRYTE
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index aaa3b833a5..30934d9cc6 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -170,13 +170,6 @@ config ANDES_PLIC
 	  The Andes PLIC block holds memory-mapped claim and pending registers
 	  associated with software interrupt.
 
-config ANDES_PLMT
-	bool
-	depends on RISCV_MMODE || SPL_RISCV_MMODE
-	help
-	  The Andes PLMT block holds memory-mapped mtime register
-	  associated with timer tick.
-
 config SYS_MALLOC_F_LEN
 	default 0x1000
 
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 10ac5b06d3..12c14f2019 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -13,7 +13,6 @@ obj-y	+= cache.o
 ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
 obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
 obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
-obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
 else
 obj-$(CONFIG_SBI) += sbi.o
 obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index f8fa4aa71f..6b8e4c9dc0 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -53,6 +53,13 @@ config ALTERA_TIMER
 	  Select this to enable a timer for Altera devices. Please find
 	  details on the "Embedded Peripherals IP User Guide" of Altera.
 
+config ANDES_PLMT
+	bool
+	depends on RISCV_MMODE || SPL_RISCV_MMODE
+	help
+	  The Andes PLMT block holds memory-mapped mtime register
+	  associated with timer tick.
+
 config ARC_TIMER
 	bool "ARC timer support"
 	depends on TIMER && ARC && CLK
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index 3a4d74b996..dd4f9cc1d4 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -5,6 +5,7 @@
 obj-y += timer-uclass.o
 obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
 obj-$(CONFIG_ALTERA_TIMER)	+= altera_timer.o
+obj-$(CONFIG_ANDES_PLMT) += andes_plmt_timer.o
 obj-$(CONFIG_ARC_TIMER)	+= arc_timer.o
 obj-$(CONFIG_AST_TIMER)	+= ast_timer.o
 obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o
diff --git a/arch/riscv/lib/andes_plmt.c b/drivers/timer/andes_plmt_timer.c
similarity index 100%
rename from arch/riscv/lib/andes_plmt.c
rename to drivers/timer/andes_plmt_timer.c
-- 
2.28.0

[PATCH v2 2/3] timer: Add _TIMER suffix to Andes PLMT Kconfig

[Sean Anderson]

This matches the naming scheme of other timer drivers.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
---

(no changes since v1)

 arch/riscv/cpu/ax25/Kconfig | 2 +-
 drivers/timer/Kconfig       | 2 +-
 drivers/timer/Makefile      | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 5cb5bb51eb..327b74e20a 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -5,7 +5,7 @@ config RISCV_NDS
 	imply CPU_RISCV
 	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
 	imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
-	imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
+	imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
 	imply SPL_CPU_SUPPORT
 	imply SPL_OPENSBI
 	imply SPL_LOAD_FIT
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 6b8e4c9dc0..80743a2551 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -53,7 +53,7 @@ config ALTERA_TIMER
 	  Select this to enable a timer for Altera devices. Please find
 	  details on the "Embedded Peripherals IP User Guide" of Altera.
 
-config ANDES_PLMT
+config ANDES_PLMT_TIMER
 	bool
 	depends on RISCV_MMODE || SPL_RISCV_MMODE
 	help
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index dd4f9cc1d4..226227c8ec 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -5,7 +5,7 @@
 obj-y += timer-uclass.o
 obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
 obj-$(CONFIG_ALTERA_TIMER)	+= altera_timer.o
-obj-$(CONFIG_ANDES_PLMT) += andes_plmt_timer.o
+obj-$(CONFIG_ANDES_PLMT_TIMER) += andes_plmt_timer.o
 obj-$(CONFIG_ARC_TIMER)	+= arc_timer.o
 obj-$(CONFIG_AST_TIMER)	+= ast_timer.o
 obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o
-- 
2.28.0

[PATCH v2 3/3] riscv: Move timer portions of SiFive CLINT to drivers/timer

[Sean Anderson]

Half of this driver is a DM-based timer driver, and half is RISC-V-specific
IPI code. Move the timer portions in with the other timer drivers. The
KConfig is not moved, since it also enables IPIs. It could also be split
into two configs, but no boards use the timer but not the IPI atm, so I
haven't split it.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
---

Changes in v2:
- Rebase onto master

 MAINTAINERS                        |  1 +
 arch/riscv/lib/sifive_clint.c      | 41 ++------------------------
 drivers/timer/Makefile             |  1 +
 drivers/timer/sifive_clint_timer.c | 47 ++++++++++++++++++++++++++++++
 4 files changed, 51 insertions(+), 39 deletions(-)
 create mode 100644 drivers/timer/sifive_clint_timer.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 5d022352c4..69a5bc3768 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -939,6 +939,7 @@ T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-riscv.git
 F:	arch/riscv/
 F:	cmd/riscv/
 F:	drivers/timer/andes_plmt_timer.c
+F:	drivers/timer/sifive_clint_timer.c
 F:	tools/prelink-riscv.c
 
 RISC-V KENDRYTE
diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
index a5572cb825..c8079dc510 100644
--- a/arch/riscv/lib/sifive_clint.c
+++ b/arch/riscv/lib/sifive_clint.c
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
+ * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  *
  * U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT).
@@ -8,19 +9,13 @@
  */
 
 #include <common.h>
-#include <clk.h>
 #include <dm.h>
-#include <timer.h>
 #include <asm/io.h>
-#include <asm/syscon.h>
+#include <asm/smp.h>
 #include <linux/err.h>
 
 /* MSIP registers */
 #define MSIP_REG(base, hart)		((ulong)(base) + (hart) * 4)
-/* mtime compare register */
-#define MTIMECMP_REG(base, hart)	((ulong)(base) + 0x4000 + (hart) * 8)
-/* mtime register */
-#define MTIME_REG(base)			((ulong)(base) + 0xbff8)
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -61,35 +56,3 @@ int riscv_get_ipi(int hart, int *pending)
 
 	return 0;
 }
-
-static u64 sifive_clint_get_count(struct udevice *dev)
-{
-	return readq((void __iomem *)MTIME_REG(dev->priv));
-}
-
-static const struct timer_ops sifive_clint_ops = {
-	.get_count = sifive_clint_get_count,
-};
-
-static int sifive_clint_probe(struct udevice *dev)
-{
-	dev->priv = dev_read_addr_ptr(dev);
-	if (!dev->priv)
-		return -EINVAL;
-
-	return timer_timebase_fallback(dev);
-}
-
-static const struct udevice_id sifive_clint_ids[] = {
-	{ .compatible = "riscv,clint0" },
-	{ }
-};
-
-U_BOOT_DRIVER(sifive_clint) = {
-	.name		= "sifive_clint",
-	.id		= UCLASS_TIMER,
-	.of_match	= sifive_clint_ids,
-	.probe		= sifive_clint_probe,
-	.ops		= &sifive_clint_ops,
-	.flags		= DM_FLAG_PRE_RELOC,
-};
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index 226227c8ec..eb5c48cc6c 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o
 obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
 obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
 obj-$(CONFIG_SANDBOX_TIMER)	+= sandbox_timer.o
+obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint_timer.o
 obj-$(CONFIG_STI_TIMER)		+= sti-timer.o
 obj-$(CONFIG_STM32_TIMER)	+= stm32_timer.o
 obj-$(CONFIG_X86_TSC_TIMER)	+= tsc_timer.o
diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/sifive_clint_timer.c
new file mode 100644
index 0000000000..00ce0f08d6
--- /dev/null
+++ b/drivers/timer/sifive_clint_timer.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <timer.h>
+#include <asm/io.h>
+#include <linux/err.h>
+
+/* mtime register */
+#define MTIME_REG(base)			((ulong)(base) + 0xbff8)
+
+static u64 sifive_clint_get_count(struct udevice *dev)
+{
+	return readq((void __iomem *)MTIME_REG(dev->priv));
+}
+
+static const struct timer_ops sifive_clint_ops = {
+	.get_count = sifive_clint_get_count,
+};
+
+static int sifive_clint_probe(struct udevice *dev)
+{
+	dev->priv = dev_read_addr_ptr(dev);
+	if (!dev->priv)
+		return -EINVAL;
+
+	return timer_timebase_fallback(dev);
+}
+
+static const struct udevice_id sifive_clint_ids[] = {
+	{ .compatible = "riscv,clint0" },
+	{ }
+};
+
+U_BOOT_DRIVER(sifive_clint) = {
+	.name		= "sifive_clint",
+	.id		= UCLASS_TIMER,
+	.of_match	= sifive_clint_ids,
+	.probe		= sifive_clint_probe,
+	.ops		= &sifive_clint_ops,
+	.flags		= DM_FLAG_PRE_RELOC,
+};
-- 
2.28.0