From mboxrd@z Thu Jan 1 00:00:00 1970 From: Leo Liang Date: Thu, 19 Nov 2020 18:27:05 +0800 Subject: [PATCH] riscv: fix the wrong swap value register In-Reply-To: <20201113114751.19340-1-brad.kim@semifive.com> References: <20201113114751.19340-1-brad.kim@semifive.com> Message-ID: <20201119102659.GA5712@andestech.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Fri, Nov 13, 2020 at 08:47:51PM +0900, Brad Kim wrote: > Not s2 register, t1 register is correct > Fortunately, it works because t1 register has a garbage value > > Signed-off-by: Brad Kim > Reviewed-by: Lukas Auer > --- > arch/riscv/cpu/start.S | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S > index bbc737ed9a..8589509e01 100644 > --- a/arch/riscv/cpu/start.S > +++ b/arch/riscv/cpu/start.S > @@ -123,7 +123,7 @@ call_board_init_f_0: > * wait for initialization to complete. > */ > la t0, hart_lottery > - li s2, 1 > + li t1, 1 > amoswap.w s2, t1, 0(t0) > bnez s2, wait_for_gd_init > #else Reviewed-by: Leo Liang