[PATCH] riscv: fix the wrong swap value register

[PATCH] riscv: fix the wrong swap value register

[Brad Kim]

Not s2 register, t1 register is correct
Fortunately, it works because t1 register has a garbage value

Signed-off-by: Brad Kim <brad.kim@semifive.com>
---
 arch/riscv/cpu/start.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index bbc737ed9a..8589509e01 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -123,7 +123,7 @@ call_board_init_f_0:
 	 * wait for initialization to complete.
 	 */
 	la	t0, hart_lottery
-	li	s2, 1
+	li	t1, 1
 	amoswap.w s2, t1, 0(t0)
 	bnez	s2, wait_for_gd_init
 #else
-- 
2.17.1

[PATCH] riscv: fix the wrong swap value register

[Lukas Auer]

On Fri, 2020-11-13 at 20:47 +0900, Brad Kim wrote:

> Not s2 register, t1 register is correct
> Fortunately, it works because t1 register has a garbage value
> 
> Signed-off-by: Brad Kim <brad.kim@semifive.com>
> ---
>  arch/riscv/cpu/start.S | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Thanks for catching this issue!

Reviewed-by: Lukas Auer <lukas@auer.io>

[PATCH] riscv: fix the wrong swap value register

[Leo Liang]

On Fri, Nov 13, 2020 at 08:47:51PM +0900, Brad Kim wrote:
> Not s2 register, t1 register is correct
> Fortunately, it works because t1 register has a garbage value
> 
> Signed-off-by: Brad Kim <brad.kim@semifive.com>
> Reviewed-by: Lukas Auer <lukas@auer.io>
> ---
>  arch/riscv/cpu/start.S | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> index bbc737ed9a..8589509e01 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -123,7 +123,7 @@ call_board_init_f_0:
>  	 * wait for initialization to complete.
>  	 */
>  	la	t0, hart_lottery
> -	li	s2, 1
> +	li	t1, 1
>  	amoswap.w s2, t1, 0(t0)
>  	bnez	s2, wait_for_gd_init
>  #else

Reviewed-by: Leo Liang <ycliang@andestech.com>

[PATCH] riscv: fix the wrong swap value register

[Rick Chen]

> From: Brad Kim [mailto:brad.kim at semifive.com]
> Sent: Friday, November 13, 2020 7:48 PM
> To: Rick Jian-Zhi Chen(???); lukas.auer at aisec.fraunhofer.de
> Cc: bmeng.cn at gmail.com; seanga2 at gmail.com; u-boot at lists.denx.de; Brad Kim
> Subject: [PATCH] riscv: fix the wrong swap value register
>
> Not s2 register, t1 register is correct
> Fortunately, it works because t1 register has a garbage value
>
> Signed-off-by: Brad Kim <brad.kim@semifive.com>
> ---
>  arch/riscv/cpu/start.S | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Rick Chen <rick@andestech.com>

> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> index bbc737ed9a..8589509e01 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -123,7 +123,7 @@ call_board_init_f_0:
>          * wait for initialization to complete.
>          */
>         la      t0, hart_lottery
> -       li      s2, 1
> +       li      t1, 1
>         amoswap.w s2, t1, 0(t0)
>         bnez    s2, wait_for_gd_init
>  #else
> --
> 2.17.1
>