From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Tue, 5 Jan 2021 07:54:03 -0500 Subject: [PATCH v2] nvme: Use only 32-bit accesses in nvme_writeq/nvme_readq In-Reply-To: <27b1d2116c1d37a261bfd6e12f82f84e3e4c079d.1609330566.git.stefan@agner.ch> References: <27b1d2116c1d37a261bfd6e12f82f84e3e4c079d.1609330566.git.stefan@agner.ch> Message-ID: <20210105125403.GE2292@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Wed, Dec 30, 2020 at 01:16:36PM +0100, Stefan Agner wrote: > There might be hardware configurations where 64-bit data accesses > to NVMe registers are not supported properly. This patch removes > the readq/writeq so always two 32-bit accesses are used to read/write > 64-bit NVMe registers, similarly as it is done in Linux kernel. > > This patch fixes operation of NVMe devices on RPi4 Broadcom BCM2711 SoC > based board, where the PCIe Root Complex, which is attached to the > system through the SCB bridge. > > Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely > the 64-bit wide register accesses initiated by the CPU are not properly > translated to a sequence of 32-bit PCIe accesses. > nvme_readq(), for example, always returns same value in upper and lower > 32-bits, e.g. 0x3c033fff3c033fff which lead to NVMe devices to fail > probing. > > This fix is analogous to commit 8e2ab05000ab ("usb: xhci: Use only > 32-bit accesses in xhci_writeq/xhci_readq"). > > Cc: Sylwester Nawrocki > Cc: Nicolas Saenz Julienne > Cc: Matthias Brugger > Reviewed-by: Stefan Roese > Reviewed-by: Bin Meng > Signed-off-by: Stefan Agner Applied to u-boot/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 659 bytes Desc: not available URL: