From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ley Foon Tan Date: Wed, 6 Jan 2021 14:04:36 +0800 Subject: [PATCH 1/2] configs: socfpga: Add CONFIG_SPL_PAD_TO Message-ID: <20210106060437.129462-1-ley.foon.tan@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Add CONFIG_SPL_PAD_TO for Gen5 and Arria 10. CONFIG_SPL_PAD_TO is set to size of OCRAM. This is preparation for image padding change in socfpgaimage. Signed-off-by: Ley Foon Tan --- include/configs/socfpga_common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 3d71759da4b4..62b327cd6e52 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -22,8 +22,10 @@ #if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE +#define CONFIG_SPL_PAD_TO 0x10000 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 +#define CONFIG_SPL_PAD_TO 0x40000 /* SPL memory allocation configuration, this is for FAT implementation */ #ifndef CONFIG_SYS_SPL_MALLOC_SIZE #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000 -- 2.19.0