From: Andre Przywara <andre.przywara@arm.com>
To: u-boot@lists.denx.de
Subject: [PATCH 3/3] net: sun8i-emac: Simplify EPHY offset calculation
Date: Mon, 11 Jan 2021 01:03:06 +0000 [thread overview]
Message-ID: <20210111010306.6872-4-andre.przywara@arm.com> (raw)
In-Reply-To: <20210111010306.6872-1-andre.przywara@arm.com>
Most SoCs using the sun8i-emac IP use a register in the "syscon" area to
control some PHY related settings. The R40 is special, since this
register is located in the CCU IP.
So far we were storing the *base* address in our priv struct, then adding
the offset later when we need to use it.
Change the code to add the offset already when we parse the DT node, so
that sysctl_reg contains the final EPHY register address.
This simplifies adding support for the two EMACs on the H616 later.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/net/sun8i_emac.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index a1a30b34579..38b6b3b08c6 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -324,16 +324,16 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
if (priv->variant == R40_GMAC) {
/* Select RGMII for R40 */
- reg = readl(priv->sysctl_reg + 0x164);
+ reg = readl(priv->sysctl_reg);
reg |= SC_ETCS_INT_GMII |
SC_EPIT |
(CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET);
- writel(reg, priv->sysctl_reg + 0x164);
+ writel(reg, priv->sysctl_reg);
return 0;
}
- reg = readl(priv->sysctl_reg + 0x30);
+ reg = readl(priv->sysctl_reg);
reg = sun8i_emac_set_syscon_ephy(priv, reg);
@@ -374,7 +374,7 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
& SC_ERXDC_MASK;
- writel(reg, priv->sysctl_reg + 0x30);
+ writel(reg, priv->sysctl_reg);
return 0;
}
@@ -916,6 +916,10 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
debug("%s: Cannot find syscon base address\n", __func__);
return -EINVAL;
}
+ if (priv->variant == R40_GMAC)
+ priv->sysctl_reg += 0x164;
+ else
+ priv->sysctl_reg += 0x30;
pdata->phy_interface = -1;
priv->phyaddr = -1;
--
2.17.5
next prev parent reply other threads:[~2021-01-11 1:03 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-11 1:03 [PATCH 0/3] sunxi: Refactoring in prepration for H616 Andre Przywara
2021-01-11 1:03 ` [PATCH 1/3] mmc: sunxi: Refactor mod clock register offset Andre Przywara
2021-01-11 1:33 ` Jaehoon Chung
2021-01-11 1:03 ` [PATCH 2/3] net: sun8i-emac: Always clear syscon EPHY register Andre Przywara
2021-01-11 1:03 ` Andre Przywara [this message]
2021-01-11 19:37 ` [PATCH 0/3] sunxi: Refactoring in prepration for H616 Jernej Škrabec
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