[PATCH 1/7] clk: aspeed: Add AST2600 clock support

Chia-Wei, Wang
2020-12-14T05:54:23Z

From: Ryan Chen <ryan_chen@aspeedtech.com>

This patch adds the clock control driver
for the AST2600 SoC.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
---
.../arm/include/asm/arch-aspeed/scu_ast2600.h | 338 +++++
drivers/clk/aspeed/Makefile | 1 +
drivers/clk/aspeed/clk_ast2600.c | 1173 +++++++++++++++++
include/dt-bindings/clock/ast2600-clock.h | 62 +
4 files changed, 1574 insertions(+)
create mode 100644 arch/arm/include/asm/arch-aspeed/scu_ast2600.h
create mode 100644 drivers/clk/aspeed/clk_ast2600.c
create mode 100644 include/dt-bindings/clock/ast2600-clock.h

diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h
new file mode 100644
index 0000000000..a205fb1f76
--- /dev/null
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h
@@ -0,0 +1,338 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) Aspeed Technology Inc.
+ */
+#ifndef _ASM_ARCH_SCU_AST2600_H
+#define _ASM_ARCH_SCU_AST2600_H
+
+#define SCU_UNLOCK_KEY 0x1688a8a8
+
+#define SCU_CLKGATE1_EMMC BIT(27)
+#define SCU_CLKGATE1_MAC2 BIT(21)
+#define SCU_CLKGATE1_MAC1 BIT(20)
+#define SCU_CLKGATE1_USB_HUB BIT(14)
+#define SCU_CLKGATE1_USB_HOST2 BIT(7)
+
+#define SCU_CLKGATE2_FSI BIT(30)
+#define SCU_CLKGATE2_MAC4 BIT(21)
+#define SCU_CLKGATE2_MAC3 BIT(20)
+#define SCU_CLKGATE2_SDIO BIT(4)
+
+#define SCU_DRAM_HDSHK_SOC_INIT BIT(7)
+#define SCU_DRAM_HDSHK_RDY BIT(6)
+
+#define SCU_CLKSRC1_ECC_RSA_DIV_MASK GENMASK(27, 26)
+#define SCU_CLKSRC1_ECC_RSA_DIV_SHIFT 26
+#define SCU_CLKSRC1_PCLK_DIV_MASK GENMASK(25, 23)
+#define SCU_CLKSRC1_PCLK_DIV_SHIFT 23
+#define SCU_CLKSRC1_BCLK_DIV_MASK GENMASK(22, 20)
+#define SCU_CLKSRC1_BCLK_DIV_SHIFT 20
+#define SCU_CLKSRC1_ECC_RSA BIT(19)
+#define SCU_CLKSRC1_MAC_DIV_MASK GENMASK(18, 16)
+#define SCU_CLKSRC1_MAC_DIV_SHIFT 16
+#define SCU_CLKSRC1_EMMC_EN BIT(15)
+#define SCU_CLKSRC1_EMMC_DIV_MASK GENMASK(14, 12)
+#define SCU_CLKSRC1_EMMC_DIV_SHIFT 12
+#define SCU_CLKSRC1_EMMC BIT(11)
+
+#define SCU_CLKSRC2_RMII12 BIT(19)
+#define SCU_CLKSRC2_RMII12_DIV_MASK GENMASK(18, 16)
+#define SCU_CLKSRC2_RMII12_DIV_SHIFT 16
+#define SCU_CLKSRC2_UART5 BIT(14)
+
+#define SCU_CLKSRC4_SDIO_EN BIT(31)
+#define SCU_CLKSRC4_SDIO_DIV_MASK GENMASK(30, 28)
+#define SCU_CLKSRC4_SDIO_DIV_SHIFT 28
+#define SCU_CLKSRC4_MAC_DIV_MASK GENMASK(26, 24)
+#define SCU_CLKSRC4_MAC_DIV_SHIFT 24
+#define SCU_CLKSRC4_RMII34_DIV_MASK GENMASK(18, 16)
+#define SCU_CLKSRC4_RMII34_DIV_SHIFT 16
+#define SCU_CLKSRC4_PCLK_DIV_MASK GENMASK(11, 9)
+#define SCU_CLKSRC4_PCLK_DIV_SHIFT 9
+#define SCU_CLKSRC4_SDIO BIT(8)
+#define SCU_CLKSRC4_UART6 BIT(5)
+#define SCU_CLKSRC4_UART4 BIT(3)
+#define SCU_CLKSRC4_UART3 BIT(2)
+#define SCU_CLKSRC4_UART2 BIT(1)
+#define SCU_CLKSRC4_UART1 BIT(0)
+
+#define SCU_CLKSRC5_UART13 BIT(12)
+#define SCU_CLKSRC5_UART12 BIT(11)
+#define SCU_CLKSRC5_UART11 BIT(10)
+#define SCU_CLKSRC5_UART10 BIT(9)
+#define SCU_CLKSRC5_UART9 BIT(8)
+#define SCU_CLKSRC5_UART8 BIT(7)
+#define SCU_CLKSRC5_UART7 BIT(6)
+#define SCU_CLKSRC5_HUXCLK_MASK GENMASK(5, 3)
+#define SCU_CLKSRC5_HUXCLK_SHIFT 3
+#define SCU_CLKSRC5_UXCLK_MASK GENMASK(2, 0)
+#define SCU_CLKSRC5_UXCLK_SHIFT 0
+
+#define SCU_PINCTRL1_EMMC_MASK GENMASK(31, 24)
+#define SCU_PINCTRL1_EMMC_SHIFT 24
+
+#define SCU_PINCTRL16_MAC4_DRIVING_MASK GENMASK(3, 2)
+#define SCU_PINCTRL16_MAC4_DRIVING_SHIFT 2
+#define SCU_PINCTRL16_MAC3_DRIVING_MASK GENMASK(1, 0)
+#define SCU_PINCTRL16_MAC3_DRIVING_SHIFT 0
+
+#define SCU_HWSTRAP1_CPU_AXI_CLK_RATIO BIT(16)
+#define SCU_HWSTRAP1_VGA_MEM_MASK GENMASK(14, 13)
+#define SCU_HWSTRAP1_VGA_MEM_SHIFT 13
+#define SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_MASK GENMASK(12, 11)
+#define SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_SHIFT 11
+#define SCU_HWSTRAP1_CPU_FREQ_MASK GENMASK(10, 8)
+#define SCU_HWSTRAP1_CPU_FREQ_SHIFT 8
+#define SCU_HWSTRAP1_MAC2_INTF BIT(7)
+#define SCU_HWSTRAP1_MAC1_INTF BIT(6)
+
+#define SCU_EFUSE_DIS_DP BIT(17)
+#define SCU_EFUSE_DIS_VGA BIT(14)
+#define SCU_EFUSE_DIS_PCIE_EP BIT(13)
+#define SCU_EFUSE_DIS_USB BIT(12)
+#define SCU_EFUSE_DIS_RVAS BIT(10)
+#define SCU_EFUSE_DIS_VIDEO_DEC BIT(9)
+#define SCU_EFUSE_DIS_VIDEO BIT(8)
+#define SCU_EFUSE_DIS_PCIE_RC BIT(7)
+#define SCU_EFUSE_DIS_CM3 BIT(6)
+#define SCU_EFUSE_DIS_CA7 BIT(5)
+
+#define SCU_PLL_RST BIT(25)
+#define SCU_PLL_BYPASS BIT(24)
+#define SCU_PLL_OFF BIT(23)
+#define SCU_PLL_DIV_MASK GENMASK(22, 19)
+#define SCU_PLL_DIV_SHIFT 19
+#define SCU_PLL_DENUM_MASK GENMASK(18, 13)
+#define SCU_PLL_DENUM_SHIFT 13
+#define SCU_PLL_NUM_MASK GENMASK(12, 0)
+#define SCU_PLL_NUM_SHIFT 0
+
+#define SCU_UART_CLKGEN_N_MASK GENMASK(17, 8)
+#define SCU_UART_CLKGEN_N_SHIFT 8
+#define SCU_UART_CLKGEN_R_MASK GENMASK(7, 0)
+#define SCU_UART_CLKGEN_R_SHIFT 0
+
+#define SCU_HUART_CLKGEN_N_MASK GENMASK(17, 8)
+#define SCU_HUART_CLKGEN_N_SHIFT 8
+#define SCU_HUART_CLKGEN_R_MASK GENMASK(7, 0)
+#define SCU_HUART_CLKGEN_R_SHIFT 0
+
+#define SCU_MISC_CTRL1_UART5_DIV BIT(12)
+
+#ifndef __ASSEMBLY__
+struct ast2600_scu {
+ uint32_t prot_key1; /* 0x000 */
+ uint32_t chip_id1; /* 0x004 */
+ uint32_t rsv_0x08; /* 0x008 */
+ uint32_t rsv_0x0c; /* 0x00C */
+ uint32_t prot_key2; /* 0x010 */
+ uint32_t chip_id2; /* 0x014 */
+ uint32_t rsv_0x18[10]; /* 0x018 ~ 0x03C */
+ uint32_t modrst_ctrl1; /* 0x040 */
+ uint32_t modrst_clr1; /* 0x044 */
+ uint32_t rsv_0x48; /* 0x048 */
+ uint32_t rsv_0x4C; /* 0x04C */
+ uint32_t modrst_ctrl2; /* 0x050 */
+ uint32_t modrst_clr2; /* 0x054 */
+ uint32_t rsv_0x58; /* 0x058 */
+ uint32_t rsv_0x5C; /* 0x05C */
+ uint32_t extrst_sel1; /* 0x060 */
+ uint32_t sysrst_sts1_1; /* 0x064 */
+ uint32_t sysrst_sts1_2; /* 0x068 */
+ uint32_t sysrst_sts1_3; /* 0x06C */
+ uint32_t extrst_sel2; /* 0x070 */
+ uint32_t sysrst_sts2_1; /* 0x074 */
+ uint32_t sysrst_sts2_2; /* 0x078 */
+ uint32_t stsrst_sts3_2; /* 0x07C */
+ uint32_t clkgate_ctrl1; /* 0x080 */
+ uint32_t clkgate_clr1; /* 0x084 */
+ uint32_t rsv_0x88; /* 0x088 */
+ uint32_t rsv_0x8C; /* 0x08C */
+ uint32_t clkgate_ctrl2; /* 0x090 */
+ uint32_t clkgate_clr2; /* 0x094 */
+ uint32_t rsv_0x98[10]; /* 0x098 ~ 0x0BC */
+ uint32_t misc_ctrl1; /* 0x0C0 */
+ uint32_t misc_ctrl2; /* 0x0C4 */
+ uint32_t debug_ctrl1; /* 0x0C8 */
+ uint32_t rsv_0xCC; /* 0x0CC */
+ uint32_t misc_ctrl3; /* 0x0D0 */
+ uint32_t misc_ctrl4; /* 0x0D4 */
+ uint32_t debug_ctrl2; /* 0x0D8 */
+ uint32_t rsv_0xdc[9]; /* 0x0DC ~ 0x0FC */
+ uint32_t dram_hdshk; /* 0x100 */
+ uint32_t soc_scratch[3]; /* 0x104 ~ 0x10C */
+ uint32_t rsv_0x110[4]; /* 0x110 ~ 0x11C*/
+ uint32_t cpu_scratch_wp; /* 0x120 */
+ uint32_t rsv_0x124[23]; /* 0x124 */
+ uint32_t smp_boot[12]; /* 0x180 */
+ uint32_t cpu_scratch[20]; /* 0x1b0 */
+ uint32_t hpll; /* 0x200 */
+ uint32_t hpll_ext; /* 0x204 */
+ uint32_t rsv_0x208[2]; /* 0x208 ~ 0x20C */
+ uint32_t apll; /* 0x210 */
+ uint32_t apll_ext; /* 0x214 */
+ uint32_t rsv_0x218[2]; /* 0x218 ~ 0x21C */
+ uint32_t mpll; /* 0x220 */
+ uint32_t mpll_ext; /* 0x224 */
+ uint32_t rsv_0x228[6]; /* 0x228 ~ 0x23C */
+ uint32_t epll; /* 0x240 */
+ uint32_t epll_ext; /* 0x244 */
+ uint32_t rsv_0x248[6]; /* 0x248 ~ 0x25C */
+ uint32_t dpll; /* 0x260 */
+ uint32_t dpll_ext; /* 0x264 */
+ uint32_t rsv_0x268[38]; /* 0x268 ~ 0x2FC */
+ uint32_t clksrc1; /* 0x300 */
+ uint32_t clksrc2; /* 0x304 */
+ uint32_t clksrc3; /* 0x308 */
+ uint32_t rsv_0x30c; /* 0x30C */
+ uint32_t clksrc4; /* 0x310 */
+ uint32_t clksrc5; /* 0x314 */
+ uint32_t rsv_0x318[2]; /* 0x318 ~ 0x31C */
+ uint32_t freq_counter_ctrl1; /* 0x320 */
+ uint32_t freq_counter_cmp1; /* 0x324 */
+ uint32_t rsv_0x328[2]; /* 0x328 ~ 0x32C */
+ uint32_t freq_counter_ctrl2; /* 0x330 */
+ uint32_t freq_counter_cmp2; /* 0x334 */
+ uint32_t uart_clkgen; /* 0x338 */
+ uint32_t huart_clkgen; /* 0x33C */
+ uint32_t mac12_clk_delay; /* 0x340 */
+ uint32_t rsv_0x344; /* 0x344 */
+ uint32_t mac12_clk_delay_100M; /* 0x348 */
+ uint32_t mac12_clk_delay_10M; /* 0x34C */
+ uint32_t mac34_clk_delay; /* 0x350 */
+ uint32_t rsv_0x354; /* 0x354 */
+ uint32_t mac34_clk_delay_100M; /* 0x358 */
+ uint32_t mac34_clk_delay_10M; /* 0x35C */
+ uint32_t clkduty_meas_ctrl; /* 0x360 */
+ uint32_t clkduty1; /* 0x364 */
+ uint32_t clkduty2; /* 0x368 */
+ uint32_t clkduty_meas_res; /* 0x36C */
+ uint32_t clkduty_meas_ctrl2; /* 0x370 */
+ uint32_t clkduty3; /* 0x374 */
+ uint32_t rsv_0x378[34]; /* 0x378 ~ 0x3FC */
+ uint32_t pinmux1; /* 0x400 */
+ uint32_t pinmux2; /* 0x404 */
+ uint32_t rsv_0x408; /* 0x408 */
+ uint32_t pinmux3; /* 0x40C */
+ uint32_t pinmux4; /* 0x410 */
+ uint32_t pinmux5; /* 0x414 */
+ uint32_t pinmux6; /* 0x418 */
+ uint32_t pinmux7; /* 0x41C */
+ uint32_t rsv_0x420[4]; /* 0x420 ~ 0x42C */
+ uint32_t pinmux8; /* 0x430 */
+ uint32_t pinmux9; /* 0x434 */
+ uint32_t pinmux10; /* 0x438 */
+ uint32_t rsv_0x43c; /* 0x43C */
+ uint32_t pinmux12; /* 0x440 */
+ uint32_t pinmux13; /* 0x444 */
+ uint32_t rsv_0x448[2]; /* 0x448 ~ 0x44C */
+ uint32_t pinmux14; /* 0x450 */
+ uint32_t pinmux15; /* 0x454 */
+ uint32_t pinmux16; /* 0x458 */
+ uint32_t rsv_0x45c[21]; /* 0x45C ~ 0x4AC */
+ uint32_t pinmux17; /* 0x4B0 */
+ uint32_t pinmux18; /* 0x4B4 */
+ uint32_t pinmux19; /* 0x4B8 */
+ uint32_t pinmux20; /* 0x4BC */
+ uint32_t rsv_0x4c0[5]; /* 0x4C0 ~ 0x4D0 */
+ uint32_t pinmux22; /* 0x4D4 */
+ uint32_t pinmux23; /* 0x4D8 */
+ uint32_t rsv_0x4dc[9]; /* 0x4DC ~ 0x4FC */
+ uint32_t hwstrap1; /* 0x500 */
+ uint32_t hwstrap_clr1; /* 0x504 */
+ uint32_t hwstrap_prot1; /* 0x508 */
+ uint32_t rsv_0x50c; /* 0x50C */
+ uint32_t hwstrap2; /* 0x510 */
+ uint32_t hwstrap_clr2; /* 0x514 */
+ uint32_t hwstrap_prot2; /* 0x518 */
+ uint32_t rsv_0x51c; /* 0x51C */
+ uint32_t rng_ctrl; /* 0x520 */
+ uint32_t rng_data; /* 0x524 */
+ uint32_t rsv_0x528[6]; /* 0x528 ~ 0x53C */
+ uint32_t pwr_save_wakeup_en1; /* 0x540 */
+ uint32_t pwr_save_wakeup_ctrl1; /* 0x544 */
+ uint32_t rsv_0x548[2]; /* 0x548 */
+ uint32_t pwr_save_wakeup_en2; /* 0x550 */
+ uint32_t pwr_save_wakeup_ctrl2; /* 0x554 */
+ uint32_t rsv_0x558[2]; /* 0x558 */
+ uint32_t intr1_ctrl_sts; /* 0x560 */
+ uint32_t rsv_0x564[3]; /* 0x564 */
+ uint32_t intr2_ctrl_sts; /* 0x570 */
+ uint32_t rsv_0x574[7]; /* 0x574 ~ 0x58C */
+ uint32_t otp_ctrl; /* 0x590 */
+ uint32_t efuse; /* 0x594 */
+ uint32_t rsv_0x598[6]; /* 0x598 */
+ uint32_t chip_unique_id[8]; /* 0x5B0 */
+ uint32_t rsv_0x5e0[8]; /* 0x5E0 ~ 0x5FC */
+ uint32_t disgpio_in_pull_down0; /* 0x610 */
+ uint32_t disgpio_in_pull_down1; /* 0x614 */
+ uint32_t disgpio_in_pull_down2; /* 0x618 */
+ uint32_t disgpio_in_pull_down3; /* 0x61C */
+ uint32_t rsv_0x620[4]; /* 0x620 ~ 0x62C */
+ uint32_t disgpio_in_pull_down4; /* 0x630 */
+ uint32_t disgpio_in_pull_down5; /* 0x634 */
+ uint32_t disgpio_in_pull_down6; /* 0x638 */
+ uint32_t rsv_0x63c[5]; /* 0x63C ~ 0x64C */
+ uint32_t sli_driving_strength; /* 0x650 */
+ uint32_t rsv_0x654[107]; /* 0x654 ~ 0x7FC */
+ uint32_t ca7_ctrl1; /* 0x800 */
+ uint32_t ca7_ctrl2; /* 0x804 */
+ uint32_t ca7_ctrl3; /* 0x808 */
+ uint32_t ca7_ctrl4; /* 0x80C */
+ uint32_t rsv_0x810[4]; /* 0x810 ~ 0x81C */
+ uint32_t ca7_parity_chk; /* 0x820 */
+ uint32_t ca7_parity_clr; /* 0x824 */
+ uint32_t rsv_0x828[118]; /* 0x828 ~ 0x9FC */
+ uint32_t cm3_ctrl; /* 0xA00 */
+ uint32_t cm3_base; /* 0xA04 */
+ uint32_t cm3_imem_addr; /* 0xA08 */
+ uint32_t cm3_dmem_addr; /* 0xA0C */
+ uint32_t rsv_0xa10[12]; /* 0xA10 ~ 0xA3C */
+ uint32_t cm3_cache_area; /* 0xA40 */
+ uint32_t cm3_cache_invd_ctrl; /* 0xA44 */
+ uint32_t cm3_cache_func_ctrl; /* 0xA48 */
+ uint32_t rsv_0xa4c[108]; /* 0xA4C ~ 0xBFC */
+ uint32_t pci_cfg[3]; /* 0xC00 */
+ uint32_t rsv_0xc0c[5]; /* 0xC0C ~ 0xC1C */
+ uint32_t pcie_cfg; /* 0xC20 */
+ uint32_t mmio_decode; /* 0xC24 */
+ uint32_t reloc_ctrl_decode[2]; /* 0xC28 */
+ uint32_t rsv_0xc30[4]; /* 0xC30 ~ 0xC3C */
+ uint32_t mbox_decode; /* 0xC40 */
+ uint32_t shared_sram_decode[2]; /* 0xC44 */
+ uint32_t bmc_rev_id; /* 0xC4C */
+ uint32_t rsv_0xc50[5]; /* 0xC50 ~ 0xC60 */
+ uint32_t bmc_device_id; /* 0xC64 */
+ uint32_t rsv_0xc68[102]; /* 0xC68 ~ 0xDFC */
+ uint32_t vga_scratch1; /* 0xE00 */
+ uint32_t vga_scratch2; /* 0xE04 */
+ uint32_t vga_scratch3; /* 0xE08 */
+ uint32_t vga_scratch4; /* 0xE0C */
+ uint32_t rsv_0xe10[4]; /* 0xE10 ~ 0xE1C */
+ uint32_t vga_scratch5; /* 0xE20 */
+ uint32_t vga_scratch6; /* 0xE24 */
+ uint32_t vga_scratch7; /* 0xE28 */
+ uint32_t vga_scratch8; /* 0xE2C */
+ uint32_t rsv_0xe30[52]; /* 0xE30 ~ 0xEFC */
+ uint32_t wr_prot1; /* 0xF00 */
+ uint32_t wr_prot2; /* 0xF04 */
+ uint32_t wr_prot3; /* 0xF08 */
+ uint32_t wr_prot4; /* 0xF0C */
+ uint32_t wr_prot5; /* 0xF10 */
+ uint32_t wr_prot6; /* 0xF18 */
+ uint32_t wr_prot7; /* 0xF1C */
+ uint32_t wr_prot8; /* 0xF20 */
+ uint32_t wr_prot9; /* 0xF24 */
+ uint32_t rsv_0xf28[2]; /* 0xF28 ~ 0xF2C */
+ uint32_t wr_prot10; /* 0xF30 */
+ uint32_t wr_prot11; /* 0xF34 */
+ uint32_t wr_prot12; /* 0xF38 */
+ uint32_t wr_prot13; /* 0xF3C */
+ uint32_t wr_prot14; /* 0xF40 */
+ uint32_t rsv_0xf44; /* 0xF44 */
+ uint32_t wr_prot15; /* 0xF48 */
+ uint32_t rsv_0xf4c[5]; /* 0xF4C ~ 0xF5C */
+ uint32_t wr_prot16; /* 0xF60 */
+};
+#endif
+#endif
diff --git a/drivers/clk/aspeed/Makefile b/drivers/clk/aspeed/Makefile
index 81764b4391..84776e5265 100644
--- a/drivers/clk/aspeed/Makefile
+++ b/drivers/clk/aspeed/Makefile
@@ -4,3 +4,4 @@
#

obj-$(CONFIG_ASPEED_AST2500) += clk_ast2500.o
+obj-$(CONFIG_ASPEED_AST2600) += clk_ast2600.o
diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c
new file mode 100644
index 0000000000..b29c5d0294
--- /dev/null
+++ b/drivers/clk/aspeed/clk_ast2600.c
@@ -0,0 +1,1173 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dm/lists.h>
+#include <linux/delay.h>
+#include <asm/arch/scu_ast2600.h>
+#include <dt-bindings/clock/ast2600-clock.h>
+#include <dt-bindings/reset/ast2600-reset.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CLKIN_25M 25000000UL
+
+/* MAC Clock Delay settings */
+#define MAC12_DEF_DELAY_1G 0x0041b75d
+#define MAC12_DEF_DELAY_100M 0x00417410
+#define MAC12_DEF_DELAY_10M 0x00417410
+#define MAC34_DEF_DELAY_1G 0x0010438a
+#define MAC34_DEF_DELAY_100M 0x00104208
+#define MAC34_DEF_DELAY_10M 0x00104208
+
+/*
+ * 3-bit encode of CPU freqeucy
+ * Some code is duplicated
+ */
+enum ast2600_cpu_freq {
+ CPU_FREQ_1200M_1,
+ CPU_FREQ_1600M_1,
+ CPU_FREQ_1200M_2,
+ CPU_FREQ_1600M_2,
+ CPU_FREQ_800M_1,
+ CPU_FREQ_800M_2,
+ CPU_FREQ_800M_3,
+ CPU_FREQ_800M_4,
+};
+
+struct ast2600_clk_priv {
+ struct ast2600_scu *scu;
+};
+
+/*
+ * Clock divider/multiplier configuration struct.
+ * For H-PLL and M-PLL the formula is
+ * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1)
+ * M - Numerator
+ * N - Denumerator
+ * P - Post Divider
+ * They have the same layout in their control register.
+ *
+ * D-PLL and D2-PLL have extra divider (OD + 1), which is not
+ * yet needed and ignored by clock configurations.
+ */
+union ast2600_pll_reg {
+ uint32_t w;
+ struct {
+ unsigned int m : 13;
+ unsigned int n : 6;
+ unsigned int p : 4;
+ unsigned int off : 1;
+ unsigned int bypass : 1;
+ unsigned int reset : 1;
+ unsigned int reserved : 6;
+ } b;
+};
+
+struct ast2600_pll_cfg {
+ union ast2600_pll_reg reg;
+ unsigned int ext_reg;
+};
+
+struct ast2600_pll_desc {
+ uint32_t in;
+ uint32_t out;
+ struct ast2600_pll_cfg cfg;
+};
+
+static const struct ast2600_pll_desc ast2600_pll_lookup[] = {
+ {
+ .in = CLKIN_25M,
+ .out = 400000000,
+ .cfg.reg.b.m = 95,
+ .cfg.reg.b.n = 2,
+ .cfg.reg.b.p = 1,
+ .cfg.ext_reg = 0x31,
+ },
+ {
+ .in = CLKIN_25M,
+ .out = 200000000,
+ .cfg.reg.b.m = 127,
+ .cfg.reg.b.n = 0,
+ .cfg.reg.b.p = 15,
+ .cfg.ext_reg = 0x3f,
+ },
+ {
+ .in = CLKIN_25M,
+ .out = 334000000,
+ .cfg.reg.b.m = 667,
+ .cfg.reg.b.n = 4,
+ .cfg.reg.b.p = 9,
+ .cfg.ext_reg = 0x14d,
+ },
+ {
+ .in = CLKIN_25M,
+ .out = 1000000000,
+ .cfg.reg.b.m = 119,
+ .cfg.reg.b.n = 2,
+ .cfg.reg.b.p = 0,
+ .cfg.ext_reg = 0x3d,
+ },
+ {
+ .in = CLKIN_25M,
+ .out = 50000000,
+ .cfg.reg.b.m = 95,
+ .cfg.reg.b.n = 2,
+ .cfg.reg.b.p = 15,
+ .cfg.ext_reg = 0x31,
+ },
+};
+
+/* divisor tables */
+static uint32_t axi_ahb_div0_table[] = {
+ 3, 2, 3, 4,
+};
+
+static uint32_t axi_ahb_div1_table[] = {
+ 3, 4, 6, 8,
+};
+
+static uint32_t axi_ahb_default_table[] = {
+ 3, 4, 3, 4, 2, 2, 2, 2,
+};
+
+extern uint32_t ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx)
+{
+ union ast2600_pll_reg pll_reg;
+ uint32_t hwstrap1;
+ uint32_t cpu_freq;
+ uint32_t mul = 1, div = 1;
+
+ switch (pll_idx) {
+ case ASPEED_CLK_APLL:
+ pll_reg.w = readl(&scu->apll);
+ break;
+ case ASPEED_CLK_DPLL:
+ pll_reg.w = readl(&scu->dpll);
+ break;
+ case ASPEED_CLK_EPLL:
+ pll_reg.w = readl(&scu->epll);
+ break;
+ case ASPEED_CLK_HPLL:
+ pll_reg.w = readl(&scu->hpll);
+ break;
+ case ASPEED_CLK_MPLL:
+ pll_reg.w = readl(&scu->mpll);
+ break;
+ }
+
+ if (!pll_reg.b.bypass) {
+ /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1)
+ * HPLL Numerator (M) = fix 0x5F when SCU500[10]=1
+ * Fixed 0xBF when SCU500[10]=0 and SCU500[8]=1
+ * SCU200[12:0] (default 0x8F) when SCU510[10]=0 and SCU510[8]=0
+ * HPLL Denumerator (N) = SCU200[18:13] (default 0x2)
+ * HPLL Divider (P) = SCU200[22:19] (default 0x0)
+ * HPLL Bandwidth Adj (NB) = fix 0x2F when SCU500[10]=1
+ * Fixed 0x5F when SCU500[10]=0 and SCU500[8]=1
+ * SCU204[11:0] (default 0x31) when SCU500[10]=0 and SCU500[8]=0
+ */
+ if (pll_idx == ASPEED_CLK_HPLL) {
+ hwstrap1 = readl(&scu->hwstrap1);
+ cpu_freq = (hwstrap1 & SCU_HWSTRAP1_CPU_FREQ_MASK) >>
+ SCU_HWSTRAP1_CPU_FREQ_SHIFT;
+
+ switch (cpu_freq) {
+ case CPU_FREQ_800M_1:
+ case CPU_FREQ_800M_2:
+ case CPU_FREQ_800M_3:
+ case CPU_FREQ_800M_4:
+ pll_reg.b.m = 0x5f;
+ break;
+ case CPU_FREQ_1600M_1:
+ case CPU_FREQ_1600M_2:
+ pll_reg.b.m = 0xbf;
+ break;
+ default:
+ pll_reg.b.m = 0x8f;
+ break;
+ }
+ }
+
+ mul = (pll_reg.b.m + 1) / (pll_reg.b.n + 1);
+ div = (pll_reg.b.p + 1);
+ }
+
+ return ((CLKIN_25M * mul) / div);
+}
+
+static uint32_t ast2600_get_hclk_rate(struct ast2600_scu *scu)
+{
+ uint32_t rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL);
+ uint32_t axi_div, ahb_div;
+ uint32_t hwstrap1 = readl(&scu->hwstrap1);
+ uint32_t cpu_freq = (hwstrap1 & SCU_HWSTRAP1_CPU_FREQ_MASK) >>
+ SCU_HWSTRAP1_CPU_FREQ_SHIFT;
+ uint32_t axi_ahb_ratio = (hwstrap1 & SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_MASK) >>
+ SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_SHIFT;
+
+ if (hwstrap1 & SCU_HWSTRAP1_CPU_AXI_CLK_RATIO) {
+ axi_ahb_div1_table[0] = axi_ahb_default_table[cpu_freq] * 2;
+ axi_div = 1;
+ ahb_div = axi_ahb_div1_table[axi_ahb_ratio];
+ } else {
+ axi_ahb_div0_table[0] = axi_ahb_default_table[cpu_freq];
+ axi_div = 2;
+ ahb_div = axi_ahb_div0_table[axi_ahb_ratio];
+ }
+
+ return (rate / axi_div / ahb_div);
+}
+
+static uint32_t ast2600_get_bclk_rate(struct ast2600_scu *scu)
+{
+ uint32_t rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL);
+ uint32_t clksrc1 = readl(&scu->clksrc1);
+ uint32_t bclk_div = (clksrc1 & SCU_CLKSRC1_BCLK_DIV_MASK) >>
+ SCU_CLKSRC1_BCLK_DIV_SHIFT;
+
+ return (rate / ((bclk_div + 1) * 4));
+}
+
+static uint32_t ast2600_get_pclk1_rate(struct ast2600_scu *scu)
+{
+ uint32_t rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL);
+ uint32_t clksrc1 = readl(&scu->clksrc1);
+ uint32_t pclk_div = (clksrc1 & SCU_CLKSRC1_PCLK_DIV_MASK) >>
+ SCU_CLKSRC1_PCLK_DIV_SHIFT;
+
+ return (rate / ((pclk_div + 1) * 4));
+}
+
+static uint32_t ast2600_get_pclk2_rate(struct ast2600_scu *scu)
+{
+ uint32_t rate = ast2600_get_hclk_rate(scu);
+ uint32_t clksrc4 = readl(&scu->clksrc4);
+ uint32_t pclk_div = (clksrc4 & SCU_CLKSRC4_PCLK_DIV_MASK) >>
+ SCU_CLKSRC4_PCLK_DIV_SHIFT;
+
+ return (rate / ((pclk_div + 1) * 2));
+}
+
+static uint32_t ast2600_get_uxclk_in_rate(struct ast2600_scu *scu)
+{
+ uint32_t rate = 0;
+ uint32_t clksrc5 = readl(&scu->clksrc5);
+ uint32_t uxclk = (clksrc5 & SCU_CLKSRC5_UXCLK_MASK) >>
+ SCU_CLKSRC5_UXCLK_SHIFT;
+
+ switch (uxclk) {
+ case 0:
+ rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL) / 4;
+ break;
+ case 1:
+ rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL) / 2;
+ break;
+ case 2:
+ rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL);
+ break;
+ case 3:
+ rate = ast2600_get_hclk_rate(scu);
+ break;
+ }
+
+ return rate;
+}
+
+static uint32_t ast2600_get_huxclk_in_rate(struct ast2600_scu *scu)
+{
+ uint32_t rate = 0;
+ uint32_t clksrc5 = readl(&scu->clksrc5);
+ uint32_t huxclk = (clksrc5 & SCU_CLKSRC5_HUXCLK_MASK) >>
+ SCU_CLKSRC5_HUXCLK_SHIFT;
+
+ switch (huxclk) {
+ case 0:
+ rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL) / 4;
+ break;
+ case 1:
+ rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL) / 2;
+ break;
+ case 2:
+ rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL);
+ break;
+ case 3:
+ rate = ast2600_get_hclk_rate(scu);
+ break;
+ }
+
+ return rate;
+}
+
+static uint32_t ast2600_get_uart_uxclk_rate(struct ast2600_scu *scu)
+{
+ uint32_t rate = ast2600_get_uxclk_in_rate(scu);
+ uint32_t uart_clkgen = readl(&scu->uart_clkgen);
+ uint32_t n = (uart_clkgen & SCU_UART_CLKGEN_N_MASK) >>
+ SCU_UART_CLKGEN_N_SHIFT;
+ uint32_t r = (uart_clkgen & SCU_UART_CLKGEN_R_MASK) >>
+ SCU_UART_CLKGEN_R_SHIFT;
+
+ return ((rate * r) / (n * 2));
+}
+
+static uint32_t ast2600_get_uart_huxclk_rate(struct ast2600_scu *scu)
+{
+ uint32_t rate = ast2600_get_huxclk_in_rate(scu);
+ uint32_t huart_clkgen = readl(&scu->huart_clkgen);
+ uint32_t n = (huart_clkgen & SCU_HUART_CLKGEN_N_MASK) >>
+ SCU_HUART_CLKGEN_N_SHIFT;
+ uint32_t r = (huart_clkgen & SCU_HUART_CLKGEN_R_MASK) >>
+ SCU_HUART_CLKGEN_R_SHIFT;
+
+ return ((rate * r) / (n * 2));
+}
+
+static uint32_t ast2600_get_sdio_clk_rate(struct ast2600_scu *scu)
+{
+ uint32_t rate = 0;
+ uint32_t clksrc4 = readl(&scu->clksrc4);
+ uint32_t sdio_div = (clksrc4 & SCU_CLKSRC4_SDIO_DIV_MASK) >>
+ SCU_CLKSRC4_SDIO_DIV_SHIFT;
+
+ if (clksrc4 & SCU_CLKSRC4_SDIO)
+ rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL);
+ else
+ rate = ast2600_get_hclk_rate(scu);
+
+ return (rate / ((sdio_div + 1) * 2));
+}
+
+static uint32_t ast2600_get_emmc_clk_rate(struct ast2600_scu *scu)
+{
+ uint32_t rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL);
+ uint32_t clksrc1 = readl(&scu->clksrc1);
+ uint32_t emmc_div = (clksrc1 & SCU_CLKSRC1_EMMC_DIV_MASK) >>
+ SCU_CLKSRC1_EMMC_DIV_SHIFT;
+
+ return (rate / ((emmc_div + 1) * 4));
+}
+
+static uint32_t ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx)
+{
+ uint32_t rate = 0;
+ uint32_t uart5_clk = 0;
+ uint32_t clksrc2 = readl(&scu->clksrc2);
+ uint32_t clksrc4 = readl(&scu->clksrc4);
+ uint32_t clksrc5 = readl(&scu->clksrc5);
+ uint32_t misc_ctrl1 = readl(&scu->misc_ctrl1);
+
+ switch (uart_idx) {
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 6:
+ if (clksrc4 & BIT(uart_idx - 1))
+ rate = ast2600_get_uart_huxclk_rate(scu);
+ else
+ rate = ast2600_get_uart_uxclk_rate(scu);
+ break;
+ case 5:
+ /*
+ * SCU0C[12] and SCU304[14] together decide
+ * the UART5 clock generation
+ */
+ if (misc_ctrl1 & SCU_MISC_CTRL1_UART5_DIV)
+ uart5_clk = 0x1 << 1;
+
+ if (clksrc2 & SCU_CLKSRC2_UART5)
+ uart5_clk |= 0x1;
+
+ switch (uart5_clk) {
+ case 0:
+ rate = 24000000;
+ break;
+ case 1:
+ rate = 192000000;
+ break;
+ case 2:
+ rate = 24000000 / 13;
+ break;
+ case 3:
+ rate = 192000000 / 13;
+ break;
+ }
+
+ break;
+ case 7:
+ case 8:
+ case 9:
+ case 10:
+ case 11:
+ case 12:
+ case 13:
+ if (clksrc5 & BIT(uart_idx - 1))
+ rate = ast2600_get_uart_huxclk_rate(scu);
+ else
+ rate = ast2600_get_uart_uxclk_rate(scu);
+ break;
+ }
+
+ return rate;
+}
+
+static ulong ast2600_clk_get_rate(struct clk *clk)
+{
+ struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong rate = 0;
+
+ switch (clk->id) {
+ case ASPEED_CLK_HPLL:
+ case ASPEED_CLK_EPLL:
+ case ASPEED_CLK_DPLL:
+ case ASPEED_CLK_MPLL:
+ case ASPEED_CLK_APLL:
+ rate = ast2600_get_pll_rate(priv->scu, clk->id);
+ break;
+ case ASPEED_CLK_AHB:
+ rate = ast2600_get_hclk_rate(priv->scu);
+ break;
+ case ASPEED_CLK_APB1:
+ rate = ast2600_get_pclk1_rate(priv->scu);
+ break;
+ case ASPEED_CLK_APB2:
+ rate = ast2600_get_pclk2_rate(priv->scu);
+ break;
+ case ASPEED_CLK_GATE_UART1CLK:
+ rate = ast2600_get_uart_clk_rate(priv->scu, 1);
+ break;
+ case ASPEED_CLK_GATE_UART2CLK:
+ rate = ast2600_get_uart_clk_rate(priv->scu, 2);
+ break;
+ case ASPEED_CLK_GATE_UART3CLK:
+ rate = ast2600_get_uart_clk_rate(priv->scu, 3);
+ break;
+ case ASPEED_CLK_GATE_UART4CLK:
+ rate = ast2600_get_uart_clk_rate(priv->scu, 4);
+ break;
+ case ASPEED_CLK_GATE_UART5CLK:
+ rate = ast2600_get_uart_clk_rate(priv->scu, 5);
+ break;
+ case ASPEED_CLK_BCLK:
+ rate = ast2600_get_bclk_rate(priv->scu);
+ break;
+ case ASPEED_CLK_SDIO:
+ rate = ast2600_get_sdio_clk_rate(priv->scu);
+ break;
+ case ASPEED_CLK_EMMC:
+ rate = ast2600_get_emmc_clk_rate(priv->scu);
+ break;
+ case ASPEED_CLK_UARTX:
+ rate = ast2600_get_uart_uxclk_rate(priv->scu);
+ break;
+ case ASPEED_CLK_HUARTX:
+ rate = ast2600_get_uart_huxclk_rate(priv->scu);
+ break;
+ default:
+ debug("can't get clk rate\n");
+ return -ENOENT;
+ }
+
+ return rate;
+}
+
+/**
+ * @brief lookup PLL divider config by input/output rate
+ * @param[in] *pll - PLL descriptor
+ * @return true - if PLL divider config is found, false - else
+ * The function caller shall fill "pll->in" and "pll->out",
+ * then this function will search the lookup table
+ * to find a valid PLL divider configuration.
+ */
+static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll)
+{
+ uint32_t i;
+ const struct ast2600_pll_desc *def_desc;
+ bool is_found = false;
+
+ for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) {
+ def_desc = &ast2600_pll_lookup[i];
+
+ if (def_desc->in == pll->in && def_desc->out == pll->out) {
+ is_found = true;
+ pll->cfg.reg.w = def_desc->cfg.reg.w;
+ pll->cfg.ext_reg = def_desc->cfg.ext_reg;
+ break;
+ }
+ }
+ return is_found;
+}
+
+static uint32_t ast2600_configure_pll(struct ast2600_scu *scu,
+ struct ast2600_pll_cfg *p_cfg, int pll_idx)
+{
+ uint32_t addr, addr_ext;
+ uint32_t reg;
+
+ switch (pll_idx) {
+ case ASPEED_CLK_HPLL:
+ addr = (uint32_t)(&scu->hpll);
+ addr_ext = (uint32_t)(&scu->hpll_ext);
+ break;
+ case ASPEED_CLK_MPLL:
+ addr = (uint32_t)(&scu->mpll);
+ addr_ext = (uint32_t)(&scu->mpll_ext);
+ break;
+ case ASPEED_CLK_DPLL:
+ addr = (uint32_t)(&scu->dpll);
+ addr_ext = (uint32_t)(&scu->dpll_ext);
+ break;
+ case ASPEED_CLK_EPLL:
+ addr = (uint32_t)(&scu->epll);
+ addr_ext = (uint32_t)(&scu->epll_ext);
+ break;
+ case ASPEED_CLK_APLL:
+ addr = (uint32_t)(&scu->apll);
+ addr_ext = (uint32_t)(&scu->apll_ext);
+ break;
+ default:
+ debug("unknown PLL index\n");
+ return 1;
+ }
+
+ p_cfg->reg.b.bypass = 0;
+ p_cfg->reg.b.off = 1;
+ p_cfg->reg.b.reset = 1;
+
+ reg = readl(addr);
+ reg &= ~GENMASK(25, 0);
+ reg |= p_cfg->reg.w;
+ writel(reg, addr);
+
+ /* write extend parameter */
+ writel(p_cfg->ext_reg, addr_ext);
+ udelay(100);
+ p_cfg->reg.b.off = 0;
+ p_cfg->reg.b.reset = 0;
+ reg &= ~GENMASK(25, 0);
+ reg |= p_cfg->reg.w;
+ writel(reg, addr);
+ while (!(readl(addr_ext) & BIT(31)))
+ ;
+
+ return 0;
+}
+
+static uint32_t ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate)
+{
+ struct ast2600_pll_desc mpll;
+
+ mpll.in = CLKIN_25M;
+ mpll.out = rate;
+ if (ast2600_search_clock_config(&mpll) == false) {
+ printf("error!! unable to find valid DDR clock setting\n");
+ return 0;
+ }
+ ast2600_configure_pll(scu, &mpll.cfg, ASPEED_CLK_MPLL);
+
+ return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL);
+}
+
+static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong new_rate;
+
+ switch (clk->id) {
+ case ASPEED_CLK_MPLL:
+ new_rate = ast2600_configure_ddr(priv->scu, rate);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return new_rate;
+}
+
+static uint32_t ast2600_configure_mac12_clk(struct ast2600_scu *scu)
+{
+ /* scu340[25:0]: 1G default delay */
+ clrsetbits_le32(&scu->mac12_clk_delay, GENMASK(25, 0),
+ MAC12_DEF_DELAY_1G);
+
+ /* set 100M/10M default delay */
+ writel(MAC12_DEF_DELAY_100M, &scu->mac12_clk_delay_100M);
+ writel(MAC12_DEF_DELAY_10M, &scu->mac12_clk_delay_10M);
+
+ /* MAC AHB = HPLL / 6 */
+ clrsetbits_le32(&scu->clksrc1, SCU_CLKSRC1_MAC_DIV_MASK,
+ (0x2 << SCU_CLKSRC1_MAC_DIV_SHIFT));
+
+ return 0;
+}
+
+static uint32_t ast2600_configure_mac34_clk(struct ast2600_scu *scu)
+{
+ /*
+ * scu350[31] RGMII 125M source: 0 = from IO pin
+ * scu350[25:0] MAC 1G delay
+ */
+ clrsetbits_le32(&scu->mac34_clk_delay, (BIT(31) | GENMASK(25, 0)),
+ MAC34_DEF_DELAY_1G);
+ writel(MAC34_DEF_DELAY_100M, &scu->mac34_clk_delay_100M);
+ writel(MAC34_DEF_DELAY_10M, &scu->mac34_clk_delay_10M);
+
+ /*
+ * clock source seletion and divider
+ * scu310[26:24] : MAC AHB bus clock = HCLK / 2
+ * scu310[18:16] : RMII 50M = HCLK_200M / 4
+ */
+ clrsetbits_le32(&scu->clksrc4,
+ (SCU_CLKSRC4_MAC_DIV_MASK | SCU_CLKSRC4_RMII34_DIV_MASK),
+ ((0x0 << SCU_CLKSRC4_MAC_DIV_SHIFT)
+ | (0x3 << SCU_CLKSRC4_RMII34_DIV_SHIFT)));
+
+ /*
+ * set driving strength
+ * scu458[3:2] : MAC4 driving strength
+ * scu458[1:0] : MAC3 driving strength
+ */
+ clrsetbits_le32(&scu->pinmux16,
+ SCU_PINCTRL16_MAC4_DRIVING_MASK | SCU_PINCTRL16_MAC3_DRIVING_MASK,
+ (0x3 << SCU_PINCTRL16_MAC4_DRIVING_SHIFT)
+ | (0x3 << SCU_PINCTRL16_MAC3_DRIVING_SHIFT));
+
+ return 0;
+}
+
+/**
+ * ast2600 RGMII clock source tree
+ * 125M from external PAD -------->|\
+ * HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2
+ * | |---->| divider |---->|/ +
+ * EPLL -->|/ |
+ * |
+ * +---------<-----------|RGMIICK PAD output enable|<-------------+
+ * |
+ * +--------------------------->|\
+ * | |----> RGMII 125M for MAC#3 & MAC#4
+ * HCLK 200M ---->|divider|---->|/
+ * To simplify the control flow:
+ * 1. RGMII 1/2 always use EPLL as the internal clock source
+ * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source
+ * 125M from external PAD -------->|\
+ * | |---->RGMII 125M for MAC#1 & MAC#2
+ * EPLL---->| divider |--->|/ +
+ * |
+ * +<--------------------|RGMIICK PAD output enable|<-------------+
+ * |
+ * +--------------------------->RGMII 125M for MAC#3 & MAC#4
+ */
+#define RGMIICK_SRC_PAD 0
+#define RGMIICK_SRC_EPLL 1 /* recommended */
+#define RGMIICK_SRC_HPLL 2
+
+#define RGMIICK_DIV2 1
+#define RGMIICK_DIV3 2
+#define RGMIICK_DIV4 3
+#define RGMIICK_DIV5 4
+#define RGMIICK_DIV6 5
+#define RGMIICK_DIV7 6
+#define RGMIICK_DIV8 7 /* recommended */
+
+#define RMIICK_DIV4 0
+#define RMIICK_DIV8 1
+#define RMIICK_DIV12 2
+#define RMIICK_DIV16 3
+#define RMIICK_DIV20 4 /* recommended */
+#define RMIICK_DIV24 5
+#define RMIICK_DIV28 6
+#define RMIICK_DIV32 7
+
+struct ast2600_mac_clk_div {
+ uint32_t src; /* 0=external PAD, 1=internal PLL */
+ uint32_t fin; /* divider input speed */
+ uint32_t n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */
+ uint32_t fout; /* fout = fin / n */
+};
+
+struct ast2600_mac_clk_div rgmii_clk_defconfig = {
+ .src = ASPEED_CLK_EPLL,
+ .fin = 1000000000,
+ .n = RGMIICK_DIV8,
+ .fout = 125000000,
+};
+
+struct ast2600_mac_clk_div rmii_clk_defconfig = {
+ .src = ASPEED_CLK_EPLL,
+ .fin = 1000000000,
+ .n = RMIICK_DIV20,
+ .fout = 50000000,
+};
+
+static void ast2600_init_mac_pll(struct ast2600_scu *p_scu,
+ struct ast2600_mac_clk_div *p_cfg)
+{
+ struct ast2600_pll_desc pll;
+
+ pll.in = CLKIN_25M;
+ pll.out = p_cfg->fin;
+ if (ast2600_search_clock_config(&pll) == false) {
+ pr_err("unable to find valid ETHNET MAC clock setting\n");
+ return;
+ }
+ ast2600_configure_pll(p_scu, &pll.cfg, p_cfg->src);
+}
+
+static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu,
+ struct ast2600_mac_clk_div *p_cfg)
+{
+ uint32_t reg_304 = readl(&p_scu->clksrc2);
+ uint32_t reg_340 = readl(&p_scu->mac12_clk_delay);
+ uint32_t reg_350 = readl(&p_scu->mac34_clk_delay);
+
+ reg_340 &= ~GENMASK(31, 29);
+ /* scu340[28]: RGMIICK PAD output enable (to MAC 3/4) */
+ reg_340 |= BIT(28);
+ if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) {
+ /*
+ * re-init PLL if the current PLL output frequency doesn't match
+ * the divider setting
+ */
+ if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src))
+ ast2600_init_mac_pll(p_scu, p_cfg);
+ /* scu340[31]: select RGMII 125M from internal source */
+ reg_340 |= BIT(31);
+ }
+
+ reg_304 &= ~GENMASK(23, 20);
+
+ /* set clock divider */
+ reg_304 |= (p_cfg->n & 0x7) << 20;
+
+ /* select internal clock source */
+ if (p_cfg->src == ASPEED_CLK_HPLL)
+ reg_304 |= BIT(23);
+
+ /* RGMII 3/4 clock source select */
+ reg_350 &= ~BIT(31);
+
+ writel(reg_304, &p_scu->clksrc2);
+ writel(reg_340, &p_scu->mac12_clk_delay);
+ writel(reg_350, &p_scu->mac34_clk_delay);
+}
+
+/**
+ * ast2600 RMII/NCSI clock source tree
+ * HPLL -->|\
+ * | |---->| divider |----> RMII 50M for MAC#1 & MAC#2
+ * EPLL -->|/
+ * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4
+ */
+static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu,
+ struct ast2600_mac_clk_div *p_cfg)
+{
+ uint32_t clksrc2 = readl(&p_scu->clksrc2);
+ uint32_t clksrc4 = readl(&p_scu->clksrc4);
+
+ if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) {
+ /*
+ * re-init PLL if the current PLL output frequency doesn't match
+ * the divider setting
+ */
+ if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src))
+ ast2600_init_mac_pll(p_scu, p_cfg);
+ }
+
+ clksrc2 &= ~(SCU_CLKSRC2_RMII12 | SCU_CLKSRC2_RMII12_DIV_MASK);
+
+ /* set RMII 1/2 clock divider */
+ clksrc2 |= (p_cfg->n & 0x7) << 16;
+
+ /* RMII clock source selection */
+ if (p_cfg->src == ASPEED_CLK_HPLL)
+ clksrc2 |= SCU_CLKSRC2_RMII12;
+
+ /* set RMII 3/4 clock divider */
+ clksrc4 &= ~SCU_CLKSRC4_RMII34_DIV_MASK;
+ clksrc4 |= (0x3 << SCU_CLKSRC4_RMII34_DIV_SHIFT);
+
+ writel(clksrc2, &p_scu->clksrc2);
+ writel(clksrc4, &p_scu->clksrc4);
+}
+
+static uint32_t ast2600_configure_mac(struct ast2600_scu *scu, int index)
+{
+ uint32_t reset_bit;
+ uint32_t clkgate_bit;
+
+ switch (index) {
+ case 1:
+ reset_bit = BIT(ASPEED_RESET_MAC1);
+ clkgate_bit = SCU_CLKGATE1_MAC1;
+ writel(reset_bit, &scu->modrst_ctrl1);
+ udelay(100);
+ writel(clkgate_bit, &scu->clkgate_clr1);
+ mdelay(10);
+ writel(reset_bit, &scu->modrst_clr1);
+ break;
+ case 2:
+ reset_bit = BIT(ASPEED_RESET_MAC2);
+ clkgate_bit = SCU_CLKGATE1_MAC2;
+ writel(reset_bit, &scu->modrst_ctrl1);
+ udelay(100);
+ writel(clkgate_bit, &scu->clkgate_clr1);
+ mdelay(10);
+ writel(reset_bit, &scu->modrst_clr1);
+ break;
+ case 3:
+ reset_bit = BIT(ASPEED_RESET_MAC3 - 32);
+ clkgate_bit = SCU_CLKGATE2_MAC3;
+ writel(reset_bit, &scu->modrst_ctrl2);
+ udelay(100);
+ writel(clkgate_bit, &scu->clkgate_clr2);
+ mdelay(10);
+ writel(reset_bit, &scu->modrst_clr2);
+ break;
+ case 4:
+ reset_bit = BIT(ASPEED_RESET_MAC4 - 32);
+ clkgate_bit = SCU_CLKGATE2_MAC4;
+ writel(reset_bit, &scu->modrst_ctrl2);
+ udelay(100);
+ writel(clkgate_bit, &scu->clkgate_clr2);
+ mdelay(10);
+ writel(reset_bit, &scu->modrst_clr2);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void ast2600_configure_rsa_ecc_clk(struct ast2600_scu *scu)
+{
+ uint32_t clksrc1 = readl(&scu->clksrc1);
+
+ /* Configure RSA clock = HPLL/3 */
+ clksrc1 |= SCU_CLKSRC1_ECC_RSA;
+ clksrc1 &= ~SCU_CLKSRC1_ECC_RSA_DIV_MASK;
+ clksrc1 |= (2 << SCU_CLKSRC1_ECC_RSA_DIV_SHIFT);
+
+ writel(clksrc1, &scu->clksrc1);
+}
+
+static ulong ast2600_enable_sdclk(struct ast2600_scu *scu)
+{
+ uint32_t reset_bit;
+ uint32_t clkgate_bit;
+
+ reset_bit = BIT(ASPEED_RESET_SD - 32);
+ clkgate_bit = SCU_CLKGATE2_SDIO;
+
+ writel(reset_bit, &scu->modrst_ctrl2);
+ udelay(100);
+ writel(clkgate_bit, &scu->clkgate_clr2);
+ mdelay(10);
+ writel(reset_bit, &scu->modrst_clr2);
+
+ return 0;
+}
+
+static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu)
+{
+ int i = 0;
+ uint32_t div = 0;
+ uint32_t rate = 0;
+ uint32_t clksrc4 = readl(&scu->clksrc4);
+
+ /*
+ * ast2600 SD controller max clk is 200Mhz
+ * use apll for clock source 800/4 = 200
+ * controller max is 200mhz
+ */
+ rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL);
+ for (i = 0; i < 8; i++) {
+ div = (i + 1) * 2;
+ if ((rate / div) <= 200000000)
+ break;
+ }
+ clksrc4 &= ~SCU_CLKSRC4_SDIO_DIV_MASK;
+ clksrc4 |= (i << SCU_CLKSRC4_SDIO_DIV_SHIFT);
+ clksrc4 |= SCU_CLKSRC4_SDIO;
+ writel(clksrc4, &scu->clksrc4);
+
+ setbits_le32(&scu->clksrc4, SCU_CLKSRC4_SDIO_EN);
+
+ return 0;
+}
+
+static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu)
+{
+ uint32_t reset_bit;
+ uint32_t clkgate_bit;
+
+ reset_bit = BIT(ASPEED_RESET_EMMC);
+ clkgate_bit = SCU_CLKGATE1_EMMC;
+
+ writel(reset_bit, &scu->modrst_ctrl1);
+ udelay(100);
+ writel(clkgate_bit, &scu->clkgate_clr1);
+ mdelay(10);
+ writel(reset_bit, &scu->modrst_clr1);
+
+ return 0;
+}
+
+static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu)
+{
+ int i = 0;
+ uint32_t div = 0;
+ uint32_t rate = 0;
+ uint32_t clksrc1 = readl(&scu->clksrc1);
+
+ /*
+ * ast2600 eMMC controller max clk is 200Mhz
+ * HPll->1/2->|\
+ * |->SCU300[11]->SCU300[14:12][1/N] +
+ * MPLL------>|/ |
+ * +----------------------------------------------+
+ * |
+ * +---------> EMMC12C[15:8][1/N]-> eMMC clk
+ */
+ rate = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL);
+ for (i = 0; i < 8; i++) {
+ div = (i + 1) * 2;
+ if ((rate / div) <= 200000000)
+ break;
+ }
+
+ clksrc1 &= ~SCU_CLKSRC1_EMMC_DIV_MASK;
+ clksrc1 |= (i << SCU_CLKSRC1_EMMC_DIV_SHIFT);
+ clksrc1 |= SCU_CLKSRC1_EMMC;
+ writel(clksrc1, &scu->clksrc1);
+
+ setbits_le32(&scu->clksrc1, SCU_CLKSRC1_EMMC_EN);
+
+ return 0;
+}
+
+static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu)
+{
+ uint32_t reset_bit;
+ uint32_t clkgate_bit;
+
+ reset_bit = BIT(ASPEED_RESET_FSI % 32);
+ clkgate_bit = SCU_CLKGATE2_FSI;
+
+ /* The FSI clock is shared between masters. If it's already on
+ * don't touch it, as that will reset the existing master.
+ */
+ if (!(readl(&scu->clkgate_ctrl2) & clkgate_bit)) {
+ debug("%s: already running, not touching it\n", __func__);
+ return 0;
+ }
+
+ writel(reset_bit, &scu->modrst_ctrl2);
+ udelay(100);
+ writel(clkgate_bit, &scu->clkgate_clr2);
+ mdelay(10);
+ writel(reset_bit, &scu->modrst_clr2);
+
+ return 0;
+}
+
+static ulong ast2600_enable_usbahclk(struct ast2600_scu *scu)
+{
+ uint32_t reset_bit;
+ uint32_t clkgate_bit;
+
+ reset_bit = BIT(ASPEED_RESET_EHCI_P1);
+ clkgate_bit = SCU_CLKGATE1_USB_HUB;
+
+ writel(reset_bit, &scu->modrst_ctrl1);
+ udelay(100);
+ writel(clkgate_bit, &scu->clkgate_ctrl1);
+ mdelay(20);
+ writel(reset_bit, &scu->modrst_clr1);
+
+ return 0;
+}
+
+static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu)
+{
+ uint32_t reset_bit;
+ uint32_t clkgate_bit;
+
+ reset_bit = BIT(ASPEED_RESET_EHCI_P2);
+ clkgate_bit = SCU_CLKGATE1_USB_HOST2;
+
+ writel(reset_bit, &scu->modrst_ctrl1);
+ udelay(100);
+ writel(clkgate_bit, &scu->clkgate_clr1);
+ mdelay(20);
+ writel(reset_bit, &scu->modrst_clr1);
+
+ return 0;
+}
+
+static int ast2600_clk_enable(struct clk *clk)
+{
+ struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case ASPEED_CLK_GATE_MAC1CLK:
+ ast2600_configure_mac(priv->scu, 1);
+ break;
+ case ASPEED_CLK_GATE_MAC2CLK:
+ ast2600_configure_mac(priv->scu, 2);
+ break;
+ case ASPEED_CLK_GATE_MAC3CLK:
+ ast2600_configure_mac(priv->scu, 3);
+ break;
+ case ASPEED_CLK_GATE_MAC4CLK:
+ ast2600_configure_mac(priv->scu, 4);
+ break;
+ case ASPEED_CLK_GATE_SDCLK:
+ ast2600_enable_sdclk(priv->scu);
+ break;
+ case ASPEED_CLK_GATE_SDEXTCLK:
+ ast2600_enable_extsdclk(priv->scu);
+ break;
+ case ASPEED_CLK_GATE_EMMCCLK:
+ ast2600_enable_emmcclk(priv->scu);
+ break;
+ case ASPEED_CLK_GATE_EMMCEXTCLK:
+ ast2600_enable_extemmcclk(priv->scu);
+ break;
+ case ASPEED_CLK_GATE_FSICLK:
+ ast2600_enable_fsiclk(priv->scu);
+ break;
+ case ASPEED_CLK_GATE_USBPORT1CLK:
+ ast2600_enable_usbahclk(priv->scu);
+ break;
+ case ASPEED_CLK_GATE_USBPORT2CLK:
+ ast2600_enable_usbbhclk(priv->scu);
+ break;
+ default:
+ pr_err("can't enable clk\n");
+ return -ENOENT;
+ }
+
+ return 0;
+}
+
+struct clk_ops ast2600_clk_ops = {
+ .get_rate = ast2600_clk_get_rate,
+ .set_rate = ast2600_clk_set_rate,
+ .enable = ast2600_clk_enable,
+};
+
+static int ast2600_clk_probe(struct udevice *dev)
+{
+ struct ast2600_clk_priv *priv = dev_get_priv(dev);
+
+ priv->scu = devfdt_get_addr_ptr(dev);
+ if (IS_ERR(priv->scu))
+ return PTR_ERR(priv->scu);
+
+ ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig);
+ ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig);
+ ast2600_configure_mac12_clk(priv->scu);
+ ast2600_configure_mac34_clk(priv->scu);
+ ast2600_configure_rsa_ecc_clk(priv->scu);
+
+ return 0;
+}
+
+static int ast2600_clk_bind(struct udevice *dev)
+{
+ int ret;
+
+ /* The reset driver does not have a device node, so bind it here */
+ ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev);
+ if (ret)
+ debug("Warning: No reset driver: ret=%d\n", ret);
+
+ return 0;
+}
+
+struct aspeed_clks {
+ ulong id;
+ const char *name;
+};
+
+static struct aspeed_clks aspeed_clk_names[] = {
+ { ASPEED_CLK_HPLL, "hpll" },
+ { ASPEED_CLK_MPLL, "mpll" },
+ { ASPEED_CLK_APLL, "apll" },
+ { ASPEED_CLK_EPLL, "epll" },
+ { ASPEED_CLK_DPLL, "dpll" },
+ { ASPEED_CLK_AHB, "hclk" },
+ { ASPEED_CLK_APB1, "pclk1" },
+ { ASPEED_CLK_APB2, "pclk2" },
+ { ASPEED_CLK_BCLK, "bclk" },
+ { ASPEED_CLK_UARTX, "uxclk" },
+ { ASPEED_CLK_HUARTX, "huxclk" },
+};
+
+int soc_clk_dump(void)
+{
+ struct udevice *dev;
+ struct clk clk;
+ unsigned long rate;
+ int i, ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu),
+ &dev);
+ if (ret)
+ return ret;
+
+ printf("Clk\t\tHz\n");
+
+ for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) {
+ clk.id = aspeed_clk_names[i].id;
+ ret = clk_request(dev, &clk);
+ if (ret < 0) {
+ debug("%s clk_request() failed: %d\n", __func__, ret);
+ continue;
+ }
+
+ ret = clk_get_rate(&clk);
+ rate = ret;
+
+ clk_free(&clk);
+
+ if (ret == -ENOTSUPP) {
+ printf("clk ID %lu not supported yet\n",
+ aspeed_clk_names[i].id);
+ continue;
+ }
+ if (ret < 0) {
+ printf("%s %lu: get_rate err: %d\n", __func__,
+ aspeed_clk_names[i].id, ret);
+ continue;
+ }
+
+ printf("%s(%3lu):\t%lu\n", aspeed_clk_names[i].name,
+ aspeed_clk_names[i].id, rate);
+ }
+
+ return 0;
+}
+
+static const struct udevice_id ast2600_clk_ids[] = {
+ { .compatible = "aspeed,ast2600-scu", },
+ { },
+};
+
+U_BOOT_DRIVER(aspeed_ast2600_scu) = {
+ .name = "aspeed_ast2600_scu",
+ .id = UCLASS_CLK,
+ .of_match = ast2600_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv),
+ .ops = &ast2600_clk_ops,
+ .bind = ast2600_clk_bind,
+ .probe = ast2600_clk_probe,
+};
diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
new file mode 100644
index 0000000000..36294a5140
--- /dev/null
+++ b/include/dt-bindings/clock/ast2600-clock.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ */
+
+#define ASPEED_CLK_GATE_ECLK 0
+#define ASPEED_CLK_GATE_GCLK 1
+#define ASPEED_CLK_GATE_MCLK 2
+#define ASPEED_CLK_GATE_VCLK 3
+#define ASPEED_CLK_GATE_BCLK 4
+#define ASPEED_CLK_GATE_DCLK 5
+#define ASPEED_CLK_GATE_LCLK 6
+#define ASPEED_CLK_GATE_YCLK 7
+#define ASPEED_CLK_GATE_LHCCLK 8
+#define ASPEED_CLK_GATE_REFCLK 9
+#define ASPEED_CLK_GATE_ESPICLK 10
+#define ASPEED_CLK_GATE_UART1CLK 11
+#define ASPEED_CLK_GATE_UART2CLK 12
+#define ASPEED_CLK_GATE_UART3CLK 13
+#define ASPEED_CLK_GATE_UART4CLK 14
+#define ASPEED_CLK_GATE_UART5CLK 15
+#define ASPEED_CLK_GATE_UART6CLK 16
+#define ASPEED_CLK_GATE_UART7CLK 17
+#define ASPEED_CLK_GATE_UART8CLK 18
+#define ASPEED_CLK_GATE_UART9CLK 19
+#define ASPEED_CLK_GATE_UART10CLK 20
+#define ASPEED_CLK_GATE_UART11CLK 21
+#define ASPEED_CLK_GATE_UART12CLK 22
+#define ASPEED_CLK_GATE_UART13CLK 23
+#define ASPEED_CLK_GATE_MAC1CLK 24
+#define ASPEED_CLK_GATE_MAC2CLK 25
+#define ASPEED_CLK_GATE_MAC3CLK 26
+#define ASPEED_CLK_GATE_MAC4CLK 27
+#define ASPEED_CLK_GATE_RSACLK 28
+#define ASPEED_CLK_GATE_SDCLK 29
+#define ASPEED_CLK_GATE_SDEXTCLK 30
+#define ASPEED_CLK_GATE_EMMCCLK 31
+#define ASPEED_CLK_GATE_EMMCEXTCLK 32
+#define ASPEED_CLK_GATE_USBUHCICLK 33
+#define ASPEED_CLK_GATE_USBPORT1CLK 34
+#define ASPEED_CLK_GATE_USBPORT2CLK 35
+#define ASPEED_CLK_GATE_FSICLK 36
+
+#define ASPEED_CLK_APLL 37
+#define ASPEED_CLK_EPLL 38
+#define ASPEED_CLK_DPLL 39
+#define ASPEED_CLK_HPLL 40
+#define ASPEED_CLK_AHB 41
+#define ASPEED_CLK_APB1 42
+#define ASPEED_CLK_APB2 43
+#define ASPEED_CLK_UART 44
+#define ASPEED_CLK_SDIO 45
+#define ASPEED_CLK_ECLK 46
+#define ASPEED_CLK_ECLK_MUX 47
+#define ASPEED_CLK_LHCLK 48
+#define ASPEED_CLK_MAC 49
+#define ASPEED_CLK_BCLK 50
+#define ASPEED_CLK_MPLL 51
+#define ASPEED_CLK_24M 52
+#define ASPEED_CLK_EMMC 53
+#define ASPEED_CLK_UARTX 54
+#define ASPEED_CLK_HUARTX 55
--
2.17.1